forksheet device

**Forksheet** is an **advanced transistor architecture that extends the nanosheet concept by placing NMOS and PMOS nanosheets side-by-side separated by a thin dielectric wall** — enabling tighter N-to-P spacing than conventional GAA and further standard cell area reduction. **Forksheet vs. GAA Nanosheet** - **GAA**: NMOS and PMOS are separate nanosheet stacks with standard isolation spacing. - **Forksheet**: N and P stacks share a common gate with a dielectric wall between them. - **Dielectric Wall**: A thin (5-10 nm) dielectric wall isolates N and P channels while allowing ~30% tighter spacing. - **Gate Structure**: Gate wraps around nanosheets on 3 sides (like a fork) — one side faces the dielectric wall. **Why It Matters** - **Area Reduction**: ~20% smaller standard cell area than GAA nanosheet. - **N-P Spacing**: Reduces N-to-P spacing from ~45 nm (GAA) to ~20 nm. - **Roadmap**: Positioned between GAA nanosheet and CFET in the device architecture roadmap (imec). **Forksheet** is **the intimate CMOS pair** — placing NMOS and PMOS nanosheets side-by-side with minimal spacing for maximum density.