foundry

A semiconductor foundry is a factory that manufactures chips other companies design: a fabless customer hands over a finished layout, and the foundry turns that design into patterned silicon wafers.\n\n```svg\n\n```\n\n**The business splits into two models.** Pure-play foundries such as TSMC, GlobalFoundries, and UMC manufacture for customers without selling competing end chips. Integrated device manufacturers such as Samsung and Intel both build their own products and offer foundry capacity to outside customers, which makes trust, firewalling, and execution discipline part of the product.\n\n**Capability comes down to process node, yield, and volume.** TSMC moved 3 nm into high-volume production in 2022 and has started 2 nm volume production; Samsung Foundry brought 3 nm gate-all-around manufacturing to market; Intel Foundry is positioning Intel 18A around RibbonFET and backside power delivery. At mature nodes, companies such as GlobalFoundries and UMC remain essential for RF, automotive, industrial, display, and mixed-signal chips where reliability and cost matter more than the smallest geometry.\n\n**The economics are brutal.** A leading-edge fab can cost tens of billions of dollars, and the EUV scanners inside it are among the most expensive production tools in the world. That capital intensity is why foundry capacity, not chip design ambition, is often the binding constraint on AI hardware supply.\n\n| Foundry | Where it is strongest | Practical position |\n|---|---|---|\n| TSMC | Leading-edge logic, scale, ecosystem | 3 nm in high volume, 2 nm entering volume |\n| Samsung Foundry | Advanced nodes, gate-all-around, memory adjacency | 3 nm GAA and advanced packaging options |\n| Intel Foundry | Western capacity, advanced packaging, Intel 18A roadmap | Strategic alternative still proving external scale |\n| GlobalFoundries | RF, automotive, embedded, mature FinFET | Differentiated 12 nm and specialty platforms |\n| UMC | Mature logic, display, automotive, industrial | Broad 14 nm and above foundry capacity |\n| SMIC | China domestic supply under export controls | Restricted advanced-node access and domestic demand |\n\n```flowchart\n{ "rows": [\n { "type": "nodes", "items": [\n { "title": "Fabless design", "sub": "architecture and layout", "tone": "neutral" }\n ] },\n { "type": "arrow" },\n { "type": "group", "title": "Foundry fab", "note": "wafer manufacturing loop", "cycle": true, "loop": "process control repeats across hundreds of steps", "items": [\n { "title": "Lithography", "sub": "pattern layers", "tone": "green" },\n { "title": "Etch", "sub": "remove material", "tone": "green" },\n { "title": "Deposition", "sub": "build films", "tone": "green" },\n { "title": "Metrology", "sub": "measure yield", "tone": "orange" }\n ] },\n { "type": "arrow" },\n { "type": "nodes", "items": [\n { "title": "OSAT package", "sub": "assemble and test", "tone": "orange" }\n ] }\n] }\n```\n\n**This is why foundries are geopolitical infrastructure.** Advanced manufacturing is concentrated in a small number of companies and sites, every modern AI accelerator depends on that capacity, and access to leading wafers has become a national industrial-policy issue.\n\n---\n\nZooming out, the whole industry sorts into three tiers by what each fab can actually build:\n\n```flowchart\n{ "rows": [\n { "type": "tier", "title": "Leading edge — 3nm and below", "items": [\n { "title": "TSMC", "sub": "~90% of leading edge", "tone": "green" },\n { "title": "Samsung Foundry", "sub": "3nm GAA, yield issues", "tone": "green" },\n { "title": "Intel Foundry", "sub": "18A, external ambitions", "tone": "green" }\n ] },\n { "type": "tier", "title": "Mature nodes — 7nm to 28nm+", "items": [\n { "title": "SMIC", "sub": "7nm without EUV", "tone": "blue" },\n { "title": "GlobalFoundries", "sub": "quit leading edge 2018", "tone": "blue" },\n { "title": "UMC", "sub": "mature nodes, autos", "tone": "blue" }\n ] },\n { "type": "tier", "title": "Specialty — analog, power, RF", "items": [\n { "title": "Tower", "sub": "analog and RF", "tone": "orange" },\n { "title": "Vanguard", "sub": "power, display drivers", "tone": "orange" },\n { "title": "X-Fab", "sub": "automotive, MEMS", "tone": "orange" }\n ] }\n]}\n```\n\n**The concentration is a learning-curve story.** A modern 2 nm-class fab costs 25 to 30 billion dollars before it prints a single production wafer, and yield ramping is a compounding-knowledge game: every wafer TSMC runs teaches it something about defect sources, and it runs more wafers than everyone else combined. That flywheel — more volume, faster learning, better yields, which attracts more customers, which funds the next node — is why the field went from roughly twenty leading-edge players in 2000 to effectively three today, with only one of them consistently executing.\n\n**The revenue mechanics are worth understanding too.** Foundries sell wafers, not chips: a leading-edge wafer now runs well north of 20,000 dollars, and the customer eats the yield risk on their own design, though process defects are on the foundry. Margins hinge on fab utilization, because the cost structure is almost entirely fixed depreciation — a fab running at 95 percent prints money while the same fab at 70 percent bleeds. This is why trailing-edge foundries like GlobalFoundries deliberately exited the node race: a fully depreciated 28 nm fab serving automotive customers on long-term contracts is a genuinely good business, arguably better risk-adjusted than chasing 2 nm.\n\n**There is also a software moat people underestimate: the PDK, or process design kit.** A fabless designer's entire toolchain — Cadence and Synopsys flows, standard-cell libraries, IP blocks from Arm and others — is validated against one foundry's process. Switching foundries means re-validating everything, which is why customers rarely leave even when they are unhappy, and why Intel Foundry's real challenge is not transistors but ecosystem maturity.\n\n**On the geopolitical angle, concentration is the headline risk.** The clustering of roughly 90 percent of leading-edge capacity on a single island is the biggest structural risk in the AI supply chain, and it is what is driving the CHIPS Act fabs in Arizona, Samsung's Texas expansion, and Japan's Rapidus bet. Read a foundry through a *utilization* lens rather than a *node* lens: because the cost is almost entirely fixed depreciation, the number that decides whether a fab prints money or bleeds is what fraction of its capacity is booked — a fully depreciated 28 nm line at 95 percent can out-earn a bleeding-edge fab at 70 percent. Every strategic move in this industry — TSMC's volume flywheel, GlobalFoundries exiting the node race, the PDK lock-in, the CHIPS Act fabs — is ultimately a different bet on keeping expensive silicon capacity full.\n