Gate All Around Transistor GAA

# Gate-All-Around (GAA) Transistors: Device Physics, Architecture & Scaling

The Gate-All-Around Field-Effect Transistor (GAA FET) represents the definitive structural transition in complementary metal-oxide-semiconductor (CMOS) logic at the 3 nm, 2 nm, and sub-2 nm nodes, superseding the three-dimensional FinFET architecture that dominated semiconductor manufacturing for over a decade. In a GAA transistor, the gate dielectric and conductive metal gate electrode wrap completely around all four surfaces of vertically stacked horizontal channel ribbons—termed nanosheets or nano-ribbons—establishing full four-sided electrostatic boundary control over carrier transport.

By enclosing the conductive channel within a closed electrostatic cylinder of metal gate potential, the GAA architecture eliminates the parasitic drain-to-substrate electric field penetration that causes severe Drain-Induced Barrier Lowering (DIBL) and sub-fin punch-through leakage in FinFETs and planar MOSFETs. Furthermore, by stacking multiple nanosheet channels vertically over the exact same footprint, GAA transistors overcome the integer fin quantization constraints of FinFETs, delivering superior drive current ($I_{on}$), subthreshold swing approaching the theoretical thermodynamic limit ($\text{SS} \to 60\,\text{mV/dec}$ at $300\,\text{K}$), and continuous layout flexibility within standard logic cells.

Structural Anatomy of a Gate-All-Around (GAA) Nanosheet FET cross-sectional cutaway detailing 4-sided gate wrap, inner spacers, and epitaxial source/drain Crystalline Bulk Silicon Substrate (p-well) Bottom Dielectric Isolation (BDI: SiO₂, t = 12 nm) Source Epi Si:P / SiGe:B Drain Epi Si:P / SiGe:B 4-Sided High-k Metal Gate (HKMG: HfO₂ + WFM + W/Ru) Silicon Nanosheet 3 (W = 35 nm, T = 5 nm) Silicon Nanosheet 2 (W = 35 nm, T = 5 nm) Silicon Nanosheet 1 (W = 35 nm, T = 5 nm) Inner Spacer (SiBCN) Inner Spacer (SiBCN) Pitch ~15 nm

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## 1. Electrostatic Scaling Physics: The Boundary Value Problem

The primary physical motivation for transitioning from FinFET to Gate-All-Around is the mathematical scaling of the natural electrostatic scaling length ($\lambda$).

### 1.1 Poisson Formulation & Scale Length Comparison
In a nanoscale metal-oxide-semiconductor channel, the electrostatic potential $\phi(x,y,z)$ is governed by the 3D Poisson equation:

$$\nabla^2 \phi(x,y,z) = \frac{\partial^2 \phi}{\partial x^2} + \frac{\partial^2 \phi}{\partial y^2} + \frac{\partial^2 \phi}{\partial z^2} = -\frac{\rho(x,y,z)}{\epsilon_{Si}}$$

Where $x$ represents the source-to-drain transport direction, $y$ the transverse width direction, and $z$ the vertical confinement direction. In the subthreshold regime ($\rho \approx 0$), solving this boundary value problem with metallic gate Dirichlet boundary conditions yields an exponential spatial potential decay characterized by the natural length scale $\lambda$:

$$\Delta \phi(x) \propto \exp\left( -\frac{x}{\lambda} \right)$$

To suppress short-channel effects (SCE), prevent punch-through, and maintain a subthreshold slope near the thermal limit, the physical gate length $L_g$ must satisfy:

$$L_g \ge \alpha \cdot \lambda \quad (\text{where } \alpha \approx 4\text{ to }5)$$
+----------------------------------------------------------------------------------------------------+
|                               ELECTROSTATIC SCALE LENGTH (λ) BY GEOMETRY                           |
+---------------------+---------------------------------------------------+--------------------------+
| ARCHITECTURE        | NATURAL SCALE LENGTH FORMULATION (λ)              | TYPICAL VALUE (EOT=0.8nm)|
+---------------------+---------------------------------------------------+--------------------------+
| Planar MOSFET       | λ_planar = √[ (ε_Si / ε_ox) · t_Si · t_ox ]       | ~ 8.5 nm (Limits Lg > 35)|
+---------------------+---------------------------------------------------+--------------------------+
| 3D FinFET           | λ_FinFET = √[ (ε_Si / 2ε_ox) · W_fin · t_ox ]     | ~ 4.2 nm (Limits Lg > 18)|
+---------------------+---------------------------------------------------+--------------------------+
| GAA Cylindrical     | λ_GAA,cyl = √[ (ε_Si / 4ε_ox) · d_wire · t_ox ]   | ~ 2.1 nm (Limits Lg > 10)|
+---------------------+---------------------------------------------------+--------------------------+
| GAA Nanosheet       | λ_GAA,ns = √[ (ε_Si / 4ε_ox) · T_ns · t_ox ]      | ~ 2.4 nm (Limits Lg > 12)|
+---------------------+---------------------------------------------------+--------------------------+

Because the GAA nanosheet bounds the potential from both the top and bottom interfaces as well as both lateral sidewalls, the effective dielectric permittivity ratio $(\epsilon_{Si} / 4\epsilon_{ox})$ shrinks the natural scale length to $\lambda \approx 2.4\,\text{nm}$. This permits aggressive physical gate length scaling down to $L_g \approx 12\text{ nm}$ while maintaining a steep subthreshold swing ($\text{SS} < 65\,\text{mV/dec}$) and Drain-Induced Barrier Lowering ($\text{DIBL} < 35\,\text{mV/V}$).

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## 2. 2D Electrostatic Potential Distribution & Volume Inversion

2D Electrostatic Potential Contours: FinFET vs. GAA Nanosheet numerical potential contour heatmaps showing sub-fin field leakage vs. 4-sided volume inversion 3D FINFET: ASYMMETRIC FIELD LEAKAGE Tri-Gate (3-Sided) Inversion Core Un-Gated Sub-Fin Bulk Silicon CORNER FIELD CROWDING & SUB-FIN LOSS Electric field lines sag into un-gated bulk substrate DIBL: 65–85 mV/V | SS: 72–78 mV/dec GAA NANOSHEET: CONCENTRIC VOLUME INVERSION 4-Sided All-Around Metal Gate Volume Inversion Centroid BDI DIELECTRIC ISOLATION BARRIER PERFECT POTENTIAL CONFINEMENT Carrier wavefunctions peak at channel center (Volume Inversion) DIBL: < 35 mV/V | SS: 63–65 mV/dec

### 2.1 The Quantum Volume Inversion Effect
When the physical nanosheet thickness $T_{ns}$ shrinks below $6\,\text{nm}$, the electrostatic inversion behavior shifts from classical surface inversion to quantum volume inversion:
1. In classical planar MOSFETs, carriers are confined strictly to a 1–2 nm thin inversion layer pressed directly against the gate dielectric interface, where they suffer catastrophic surface roughness scattering ($\mu_{eff} \propto E_{eff}^{-0.3}$).
2. In GAA nanosheets with symmetric top and bottom gates, the inversion charge carriers (electrons in NMOS, holes in PMOS) occupy standing quantum states whose ground-state wavefunctions $|\psi_1(z)|^2$ peak at the exact spatial center of the silicon ribbon ($z = T_{ns} / 2$).
3. Because the peak carrier density is physically separated from the rough $\text{Si}/\text{HfO}_2$ interfacial oxide boundaries by several nanometers, surface roughness scattering is dramatically suppressed, elevating low-field carrier mobility and raising drive current density.

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## 3. Quantum Confinement & Sub-Band Energy Splitting

In ultra-thin nanosheets ($T_{ns} \le 5\,\text{nm}$), quantum confinement modifies the silicon conduction band structure, which consists of six equivalent ellipsoidal energy valleys in bulk silicon:

$$\Delta E_n = \frac{\hbar^2 \pi^2 n^2}{2 m_z^* T_{ns}^2}$$

On a standard $(001)$ silicon wafer with transport along $\langle 110 \rangle$:
- Two $\Delta_2$ Valleys: The heavy longitudinal effective mass ($m_z^* = m_l = 0.98 m_0$) aligns along the confinement axis ($z$). Consequently, their quantization energy shift $\Delta E(\Delta_2)$ is small.
- Four $\Delta_4$ Valleys: The light transverse effective mass ($m_z^* = m_t = 0.19 m_0$) aligns along the confinement axis. Their quantization energy shift $\Delta E(\Delta_4)$ is large:

$$\Delta E(\Delta_4) - \Delta E(\Delta_2) \approx \frac{\hbar^2 \pi^2}{2 T_{ns}^2} \left( \frac{1}{m_t} - \frac{1}{m_l} \right) \approx 120\text{ to }160\,\text{meV}$$

Because this energy splitting exceeds the thermal energy at room temperature ($k_B T \approx 25.9\,\text{meV}$), electrons preferentially populate the lowest-energy $\Delta_2$ sub-bands. These $\Delta_2$ electrons possess light transverse transport mass ($m_x^* = m_t = 0.19 m_0$) along the transport direction, increasing the source injection velocity ($v_{inj}$):

$$v_{inj} = \sqrt{\frac{2 k_B T}{\pi m_x^*}} \approx 1.3 \times 10^7\,\text{cm/s}$$

This represents an intrinsic $20\%\text{ to }30\%$ boost in ballistic carrier injection velocity over bulk silicon.

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## 4. Key Architectural Variations of GAA Technology

+----------------------------------------------------------------------------------------------------+
|                                    GAA ARCHITECTURAL COMPARISON                                    |
+----------------------+--------------------+--------------------+-------------------+---------------+
| PARAMETER            | GAA NANOWIRE       | GAA NANOSHEET      | FORKSHEET FET     | CFET          |
+----------------------+--------------------+--------------------+-------------------+---------------+
| Geometry             | Cylindrical Wire   | Wide 2D Ribbon     | Tri-Gate with     | 3D Vertically |
|                      | D ~ 5 nm           | W: 20-55 nm, T: 5nm| Dielectric Wall   | Stacked N/P   |
+----------------------+--------------------+--------------------+-------------------+---------------+
| Gate Wrap Topology   | 4-Sided Cylindrical| 4-Sided Planar     | 3-Sided Abutting  | Dual 4-Sided  |
|                      | Full Perimeter     | Full Wrap          | Dielectric Barrier| Independent   |
+----------------------+--------------------+--------------------+-------------------+---------------+
| Standard Cell Height | 5.5T – 6.0T        | 5.0T – 4.5T        | 4.3T – 4.0T       | 3.0T – 3.5T   |
+----------------------+--------------------+--------------------+-------------------+---------------+
| Drive Current (Ion)  | Low (Restricted    | High (+30-40% vs.  | Moderate-High     | Extremely High|
|                      | perimeter area)    | FinFET baseline)   | (Low gate cap)    | (2x per area) |
+----------------------+--------------------+--------------------+-------------------+---------------+
| Commercial Status    | Research / Niche   | High-Volume Prod.  | Advanced Pilot    | 2028-2030+    |
|                      | Demonstrators      | (TSMC N2, SF3, A16)| Line Trials       | Target Roadmap|
+----------------------+--------------------+--------------------+-------------------+---------------+

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## 5. Technology Comparison: Planar, FinFET, and GAA Across Nodes

+----------------------------------------------------------------------------------------------------+
|                               CROSS-GENERATIONAL CMOS SCALING MATRIX                               |
+----------------------+---------------------+-----------------------+-------------------------------+
| PARAMETER            | 28nm PLANAR CMOS    | 7nm / 5nm FINFET      | 2nm / A16 GAA NANOSHEET       |
+----------------------+---------------------+-----------------------+-------------------------------+
| Gate Control Sides   | 1-Sided (Top only)  | 3-Sided (Tri-gate)    | 4-Sided (All-around wrap)     |
+----------------------+---------------------+-----------------------+-------------------------------+
| Subthreshold Swing   | 85 to 105 mV/dec    | 68 to 74 mV/dec       | 62 to 65 mV/dec               |
| (SS @ short Lg)      | (Severe punch-thru) | (Drain leakage loss)  | (Near thermodynamic limit)    |
+----------------------+---------------------+-----------------------+-------------------------------+
| DIBL Metric          | > 120 mV/V          | 55 to 75 mV/V         | < 35 mV/V                     |
+----------------------+---------------------+-----------------------+-------------------------------+
| Width Quantization   | Continuous (W)      | Discrete (Integer Fin)| Continuous (W_ns mask tuning) |
+----------------------+---------------------+-----------------------+-------------------------------+
| Channel Conduction   | Bulk Sub-surface    | Volume/Surface Mix    | Quantum Volume Inversion      |
+----------------------+---------------------+-----------------------+-------------------------------+
| Sub-Fin Leakage      | Extremely high      | Moderate to high      | Extinguished (via BDI)        |
+----------------------+---------------------+-----------------------+-------------------------------+
| Backside Power Rail  | Incompatible        | Difficult / High risk | Standard Foundry Baseline     |
+----------------------+---------------------+-----------------------+-------------------------------+

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