gate-first process

**Gate-First Process** is a **HKMG integration scheme where the high-k dielectric and metal gate are deposited before the source/drain activation anneal** — meaning the gate stack must survive temperatures of 1000°C+ during the subsequent S/D dopant activation. **What Is Gate-First?** - **Flow**: Gate oxide (high-k) -> Metal gate -> Poly cap -> S/D implant -> Activation anneal (1000°C+) -> Silicide -> BEOL. - **Challenge**: High-k and metal gate materials may degrade, crystallize, or interdiffuse at 1000°C+. - **Advantage**: Simpler process flow (fewer steps than gate-last). Compatible with conventional self-aligned architecture. **Why It Matters** - **Adopted by**: Intel (45nm/32nm). IBM consortium initially used gate-first. - **Thermal Stability**: Requires gate stack materials that withstand high-temperature S/D anneal. - **Work Function Shift**: The work function can shift during high-T anneal, complicating $V_t$ targeting. **Gate-First** is **the traditional approach to HKMG** — simpler but constrained by the gate stack's ability to survive the extreme heat of dopant activation.