h-tree

**An H-tree** is a **symmetric, fractal-like clock distribution topology** that delivers the clock signal with inherently balanced delay to all endpoints — named for its characteristic "H" branching pattern at each level of the hierarchy. **H-Tree Structure** - Start with a single clock source at the center of the chip (or clock domain). - **Level 1**: The wire splits into two equal branches going left and right — forming a horizontal line. - **Level 2**: Each endpoint splits into two vertical branches going up and down — forming the letter "H". - **Level 3**: Each of those four endpoints splits horizontally again. - **Level 4**: Each of the eight endpoints splits vertically. - This continues until the tree reaches all target flip-flop clusters. **Why the H-Tree Achieves Balance** - At every branching point, both children have **identical wire length** and **identical load** (because the tree is symmetric). - The total path length from root to any leaf is the **same** for every leaf — producing zero structural skew. - This is possible because the H-tree's fractal geometry perfectly tiles a rectangular area with equal-length paths. **H-Tree Properties** - **Wire Length per Level**: Each successive level uses wires that are **half the length** of the previous level. - **Number of Endpoints**: $2^n$ endpoints at level $n$ — Level 1: 2, Level 2: 4, Level 3: 8, etc. - **Total Wire Length**: Approximately $O(N \cdot \sqrt{A})$ where $N$ is the number of endpoints and $A$ is the area. - **Branching Factor**: Always 2 (binary tree) — each node drives exactly two children. **Advantages** - **Inherent Balance**: The topology itself guarantees matched path lengths — no need for delay tuning or serpentine routing. - **Predictable**: Performance is easy to analyze and simulate. - **Scalable**: Works for any power-of-2 number of endpoints by adding levels. **Limitations** - **Rigid Geometry**: Requires a regular, symmetric floorplan — not practical when flip-flops are unevenly distributed (which is the typical case in real designs). - **Area Overhead**: The fixed branching pattern may not align with placement — wasting routing resources. - **Sensitivity to Load Imbalance**: If the flip-flop clusters at different leaves have different capacitive loads, the structural balance is broken and skew appears. - **Modern Alternative**: In practice, **CTS tools** build non-uniform trees that adapt to actual flip-flop placement — achieving better skew than a rigid H-tree in most real designs. **Where H-Trees Are Used** - **FPGAs**: The fixed, regular structure of FPGA fabrics is ideal for H-tree clock distribution. - **Memory Arrays**: Regular SRAM/DRAM arrays with symmetric layout use H-tree or H-tree-like clock structures. - **Textbook/Academic**: H-trees are the classic reference topology for understanding balanced clock distribution. The H-tree is the **foundational concept** of balanced clock distribution — while modern CTS tools build more sophisticated trees, the H-tree's principle of equal-path-length branching remains the guiding design philosophy.