handle wafer

**Handle Wafer** is the **thick, mechanical support substrate in an SOI wafer stack** — providing structural rigidity during processing while the thin device layer (where transistors are built) sits on top of the buried oxide. **What Is the Handle Wafer?** - **Material**: Standard CZ-grown bulk silicon (typically 675 $mu m$ thick for 300mm wafers). - **Quality**: Does not need to be device-grade. Resistivity and defect specs are relaxed compared to the device layer. - **Role**: Pure mechanical support. No active devices are built in the handle wafer. - **Back-Bias**: In FD-SOI, the handle wafer can serve as a back-gate electrode for body biasing. **Why It Matters** - **Cost**: Can use cheaper, lower-grade silicon for the handle — reducing overall SOI wafer cost. - **Thermal Path**: Heat from device layer conducts through BOX and handle to the package (BOX is a thermal bottleneck). - **Special Variants**: High-resistivity handle wafers (>1 k$Omega$·cm) are used for RF-SOI to minimize substrate losses. **Handle Wafer** is **the foundation of the SOI stack** — the strong, silent base that holds everything together while contributing no active electronics.