HBM
# HBM Spare TSV Redundancy for Stacking Yield
An HBM stack contains thousands of through-silicon vias running vertically through every DRAM die, and because stacking and bonding eight or more dies together multiplies the chances that at least one via somewhere in the stack has a defect, HBM designs build in spare TSVs specifically so that a single bad via doesn't scrap an otherwise-good multi-die stack. Each TSV is a microscopic vertical connection drilled and filled through silicon, and the stacking and bonding process that joins dies together introduces real opportunities for a via to end up with a void, a crack, or a poor electrical connection. With thousands of TSVs per die and many dies per stack, the overall probability that every single via across the whole stack is defect-free drops fast as stack height increases — which is exactly the yield problem spare TSVs exist to solve.
The redundancy scheme works by routing each critical signal through a spare, unused TSV instead of the defective one, using programmable switching logic in the base die to redirect connections after a defect is detected during test — meaning a single bad via becomes a repairable fault instead of a stack-scrapping defect. Rather than treating every TSV as a fixed, single point of failure, the design includes extra vias beyond the minimum needed, and test circuitry identifies which TSVs are actually working after the stack is assembled. The base die's switching logic then permanently routes each signal through a known-good via — defective or marginal, spare or primary — turning what would otherwise be a catastrophic single-point failure into a configuration decision made once during test and locked in for the stack's working life.
The number of spare TSVs included is itself an economic tradeoff: more spares improve the odds that a stack with multiple defective vias can still be repaired, but every spare TSV consumes die area and adds routing complexity that a defect-free stack never actually needs. Designers size the spare pool based on measured defect rates from the actual manufacturing process, balancing the yield recovery a given number of spares delivers against the area and complexity cost of including vias that, on a perfectly manufactured stack, would simply never be used — a classic redundancy-design tradeoff familiar from memory array sparing, applied here to the vertical interconnect itself rather than to the memory cells.
The base die's logic already handles TSV routing and request translation as its core job; spare-TSV redundancy is one specific, consequential use of that routing capability — turning what would otherwise be an unforgiving all-or-nothing stacking yield problem into a recoverable, test-time repair decision, and directly explaining why HBM stacking yield has improved as spare-via schemes have matured alongside the stacking process itself.