heterogeneous integration 3d

**Heterogeneous Integration** — combining different types of dies (logic, memory, analog, photonics, MEMS) with different process technologies into a single package, maximizing system performance beyond what any single die could achieve. **Packaging Hierarchy** - **2D**: Dies side-by-side on organic substrate (traditional multi-chip module) - **2.5D**: Dies side-by-side on silicon interposer (CoWoS, EMIB). High-bandwidth lateral interconnect - **3D**: Dies stacked vertically with TSVs or hybrid bonding. Shortest interconnect, highest density **Key Technologies** - **CoWoS (TSMC)**: 2.5D interposer. Powers NVIDIA H100/H200, AMD MI300 - **Foveros (Intel)**: 3D face-to-face stacking with hybrid bonding - **SoIC (TSMC)**: 3D wafer-on-wafer stacking - **HBM (High Bandwidth Memory)**: Memory die stacks connected to logic via interposer **Why Heterogeneous Integration?** - DRAM process ≠ logic process ≠ analog process — can't make them all on one die optimally - HBM stacks: 12-16 DRAM dies stacked with TSVs → 1 TB/s bandwidth per stack - Combine 3nm compute + 7nm I/O + 28nm analog in one package **Challenges** - Thermal management (3D stacking creates hot spots) - Testing individual chiplets before assembly - Warpage and stress management - Cost: Advanced packaging can cost more than the dies themselves **Heterogeneous integration** is now the primary scaling vector — packaging innovation increasingly matters more than transistor shrinking.