human body model (hbm)

**Human Body Model (HBM)** is the **most widely used Electrostatic Discharge (ESD) test standard** — simulating the electrical discharge that occurs when a statically charged human being touches an IC pin, modeled as a 100 pF capacitor discharging through a 1500-ohm resistor into the device, producing a fast high-current pulse that stresses ESD protection structures and determines a component's robustness to handling-induced ESD events. **What Is the Human Body Model?** - **Physical Basis**: A person walking on carpet can accumulate 10,000-25,000 volts of static charge stored in body capacitance of approximately 100-200 pF — touching an IC pin discharges this stored energy through body resistance (~1000-2000 ohms) into the device. - **Circuit Model**: Standardized as a 100 pF capacitor (human body capacitance) charging to test voltage V, then discharging through 1500-ohm series resistor (human body resistance) into the device under test (DUT). - **Waveform**: Current pulse with ~2-10 ns rise time, ~150 ns decay time — peak current of ~0.67 A per kilovolt of test voltage. - **Standard**: ANSI/ESDA/JEDEC JS-001 (Joint Standard for ESD Sensitivity) — harmonized standard replacing older military MIL-STD-883 Method 3015. **Why HBM Testing Matters** - **Universal Specification**: Every semiconductor datasheet includes HBM rating — customers require minimum HBM levels for product acceptance in manufacturing environments. - **Supply Chain Protection**: Components travel through multiple handlers from wafer fabrication through assembly, testing, and board mounting — each touch is a potential ESD event. - **Manufacturing Environment**: Even ESD-controlled facilities cannot eliminate all human contact — HBM specification defines minimum acceptable robustness for the controlled environment. - **Automotive and Industrial**: Mission-critical applications require HBM Class 2 (2 kV) or Class 3 (4+ kV) — ensuring robustness in harsh handling and installation environments. - **Design Validation**: HBM testing reveals weaknesses in ESD protection circuit design — failures guide improvements to clamp sizes, guard rings, and protection topologies. **HBM Classification System** | HBM Class | Voltage Range | Application | |-----------|--------------|-------------| | **Class 0** | < 250V | Most sensitive ICs — requires special handling | | **Class 1A** | 250-500V | Highly sensitive — controlled environments | | **Class 1B** | 500-1000V | Sensitive — standard ESD precautions | | **Class 1C** | 1000-2000V | Moderate — typical commercial IC target | | **Class 2** | 2000-4000V | Robust — standard for most applications | | **Class 3A** | 4000-8000V | High robustness — automotive/industrial | | **Class 3B** | > 8000V | Very high robustness — special applications | **HBM Test Procedure** **Test Setup**: - Charge 100 pF capacitor to target voltage V. - Connect through 1500-ohm resistor to device pin under test. - Discharge and measure resulting waveform — verify rise time and decay match standard waveform. - Test all pin combinations: each pin stressed as anode, all other pins grounded (and vice versa). **Pin Combination Matrix**: - VDD pins stressed positive, all other pins to GND. - VSS pins stressed positive, all other pins to GND. - I/O pins stressed positive and negative, power and ground pins to supply/GND. - Typical 100-pin device requires 10,000+ individual stress events for complete coverage. **Pass/Fail Criteria**: - Measure key electrical parameters before and after ESD stress. - Parametric shift threshold: typically ±10% or ±10 mV depending on parameter. - Functional test: device must operate correctly after ESD stress. - Catastrophic failure: short circuit, open circuit, or parametric failure outside limits. **HBM ESD Protection Design** **Protection Circuit Elements**: - **ESD Clamps**: Grounded gate NMOS or SCR clamps triggering at VDD+0.5V — shunt large ESD currents. - **Rail Clamps**: VDD-to-VSS clamps protecting power supply pins — largest single clamp in the design. - **Diode Networks**: Forward-biased diodes routing ESD current from I/O pins to power rails. - **Resistors**: Ballast resistors limiting current density through transistors — prevent snapback. **Design Rules for HBM Robustness**: - ESD protection transistor width scales with pin drive strength — 100 µm/mA typical. - Minimum distance between protection clamp and protected circuit — discharge must reach clamp before stressing thin-oxide circuits. - Guard rings isolating sensitive circuits — prevent latch-up triggered by ESD events. - ESD design flow: schematic (clamp placement) → layout (routing, guard rings) → simulation (SPICE verification) → silicon verification (HBM test). **HBM vs. Other ESD Models** | Model | Capacitance | Resistance | Rise Time | Represents | |-------|-------------|-----------|-----------|-----------| | **HBM** | 100 pF | 1500 Ω | 2-10 ns | Human handling | | **MM (Machine Model)** | 200 pF | 0 Ω | < 1 ns | Automated equipment (obsolete) | | **CDM (Charged Device Model)** | Variable | ~1 Ω | < 0.5 ns | Device charges and discharges | | **FICDM** | Variable | ~1 Ω | < 0.5 ns | Field-induced CDM | **Tools and Standards** - **Teradyne / Dito ESD Testers**: Automated HBM testers with pin matrix and parametric verification. - **ANSI/ESDA/JEDEC JS-001**: Current harmonized HBM standard. - **ESD Association (ESDA)**: Technical standards, training, and certification for ESD control programs. - **ESD Simulation Tools**: Mentor Calibre ESD, Synopsys CustomSim — SPICE-based ESD verification before silicon. Human Body Model is **the human touch test** — the standardized quantification of how much electrostatic discharge from human handling a semiconductor device can survive, balancing the physics of human electrostatics with the requirements of robust, manufacturable semiconductor products.