hydrogen anneal

**Hydrogen Anneal and Interface Trap Passivation** is the **post-fabrication thermal treatment that passivates electrically active defects at the Si/SiO₂ (and other dielectric) interfaces** — with hydrogen atoms diffusing from forming gas (H₂/N₂ mixture) or SiN cap to react with dangling silicon bonds (Pb centers) at the interface, converting them from electrically active traps (which degrade subthreshold slope, increase 1/f noise, and reduce drive current) into neutral Si-H bonds. **Interface Trap Physics** - Si/SiO₂ interface: Not atomically perfect → dangling Si bonds (unsatisfied bonds) → P_b centers. - P_b center density without passivation: ~10¹² – 10¹³ /cm² → high — each one is a discrete trap state. - Electrical effects: - Interface traps capture/release carriers → slow Vth drift (hysteresis). - Traps slow down carrier transit → lower effective mobility (μ_eff reduction 10–30%). - 1/f noise: Traps capture/release carriers randomly → fluctuating current → flicker noise. - Subthreshold slope: Trap-induced interface charge → Δ in subthreshold swing. **Forming Gas Anneal (FGA)** - Forming gas: 5–10% H₂ in N₂ → safe hydrogen source (diluted). - Temperature: 400–450°C for 30 minutes → sufficient for H diffusion through oxide. - Mechanism: H₂ dissociates at oxide surface or trap sites → atomic H diffuses to Si/SiO₂ interface → reacts: Si• + H → Si-H. - Result: Dit reduced from 10¹² to 10¹⁰ /cm²/eV → 100× passivation. - Gate oxide trap passivation: H₂ also passivates E' centers in SiO₂ → reduces fixed oxide charge. **SiN Hydrogen Source** - SiN cap layer (deposited by PECVD) contains large H concentration (15–25 at%). - During subsequent thermal steps (600–900°C): H released from SiN → diffuses to underlying dielectric → passivates interface traps. - Self-passivating: SiN acts as solid hydrogen reservoir → no separate FGA step needed if SiN present. - Important for: Poly gate passivation before SiN spacer forms → subsequent anneal passivates gate oxide interface. **NBTI and H De-passivation** - NBTI (Negative Bias Temperature Instability): Stress re-breaks Si-H bonds → H released → Di_t increases → ΔVth. - FGA passivates → NBTI creates traps → FGA-like recovery → NBTI has partial recovery when stress removed. - Trap annealing temperature: 200°C can partially re-passivate NBTI traps → device self-heals at low T. - High-frequency NBTI: Si-H bond breaking at fast timescales → affects circuits switching at GHz. **High-k Dielectric Interface Passivation** - HfO₂/IL (interfacial layer) interface: Not as clean as thermal SiO₂ → more interface traps. - IL (interfacial layer, ~0.5–1 nm SiO₂): Grown between HfO₂ and Si → reduces Dit significantly. - FGA at 400°C: Still effective for HfO₂/SiO₂/Si → passivates IL/Si interface. - HfO₂ bulk traps: Oxygen vacancies → not easily passivated by H₂ → separate engineering (La incorporation). **Measurement of Interface Trap Density** - **Conductance method (Nicollian-Goetzberger)**: Measure MOS capacitor conductance vs frequency vs Vg → extract Dit spectrum. - **Charge pumping**: Gate pulse transistor on/off → excess recombination current ∝ Dit. - **Low-frequency CV**: Compare ideal CV vs measured → flat-band voltage shift → density of slow traps. - Target: Dit < 2×10¹⁰ /cm²/eV at midgap for quality gate oxide. **Ammonia Nitridation Interaction** - NH₃ nitridation of SiO₂: Incorporates N at Si/SiO₂ interface → blocks B diffusion from gate. - N replaces some O → creates N-H bonds at interface → more precursors for H passivation. - Dual effect: N reduces NBTI susceptibility (slows H diffusion) AND H passivates initial traps. Hydrogen anneal and interface trap passivation are **the final defect healing step that converts a fabricated MOS structure from a defect-laden, trap-dominated device to a near-ideal transistor** — by diffusing hydrogen to the Si/SiO₂ interface and capping dangling bonds that would otherwise scatter carriers, reduce mobility, and cause Vth instability, forming gas annealing has been an indispensable post-metallization step since the 1960s and remains critical even for modern high-k/metal gate devices where interface quality directly determines subthreshold slope, 1/f noise floor, and NBTI lifetime of transistors that must operate reliably for a decade in automotive and telecommunications applications.