impedance matching

**Impedance matching** is the practice of designing the **source impedance, transmission line impedance, and load impedance** to be equal — ensuring maximum power transfer, minimum signal reflections, and optimal signal quality at high frequencies. **Why Impedance Matching Is Critical** - At high frequencies (when signal wavelength approaches wire length), the wire behaves as a **transmission line** with characteristic impedance $Z_0$. - Any mismatch between $Z_0$ and the impedances at each end causes **reflections** — energy bouncing back and forth, creating ringing, overshoot, and signal distortion. - For digital signals, mismatches that cause the signal to momentarily cross logic thresholds result in **false transitions** (glitches) and data errors. - The **rule of thumb**: impedance matching matters when the signal rise time is less than twice the propagation delay of the interconnect. **Characteristic Impedance ($Z_0$)** - Determined by the trace geometry and surrounding dielectric: $$Z_0 = \sqrt{\frac{L}{C}}$$ Where $L$ is inductance per unit length and $C$ is capacitance per unit length. - **Microstrip** (trace on surface with one ground plane): $Z_0$ typically 40–70Ω. Depends on trace width, height above ground, and dielectric constant. - **Stripline** (trace between two ground planes): $Z_0$ typically 40–60Ω. Better shielding and controlled impedance. - Common targets: **50Ω** single-ended, **100Ω** differential. **Matching Techniques** - **Source Matching (Series Termination)**: - Place a series resistor at the driver: $R_s + R_{driver} = Z_0$. - The signal launches at half amplitude, reaches full amplitude at the receiver (due to open-circuit reflection), and no further reflections occur. - **Pros**: Low power, simple. - **Cons**: Signal at half amplitude during propagation, slower for long lines. - **Load Matching (Parallel Termination)**: - Place a parallel resistor at the receiver: $R_L = Z_0$. - Signal arrives at full amplitude with no reflection. - **Pros**: Clean signal at receiver, fast settling. - **Cons**: DC current draws power. - **Differential Matching**: - Place a resistor between the differential pair at the receiver: $R_{diff} = Z_{diff}$. - Standard for high-speed interfaces (LVDS, PCIe, DDR). - **On-Die Termination (ODT)**: - Termination resistors integrated on the chip itself. - Used in DDR memory interfaces — the memory controller enables ODT on receiving devices. - Adjustable resistance (e.g., 40Ω, 60Ω, 120Ω) selected via configuration registers. **PCB Design for Impedance Control** - **Stack-Up Design**: Choose dielectric thickness and trace widths to achieve target $Z_0$. - **Controlled Impedance Manufacturing**: PCB fabricators control trace width and dielectric to ±10% impedance tolerance. - **TDR Verification**: Use time-domain reflectometry to verify manufactured impedance. **Semiconductor Applications** - **High-Speed I/O**: SerDes, DDR, PCIe, USB — all require carefully matched transmission paths. - **On-Die Interconnects**: At advanced nodes, long on-die routes (clock, bus) may need impedance-aware design. - **Package Design**: Package traces and via transitions must maintain impedance continuity. Impedance matching is the **foundation of high-speed design** — it is the first and most important step in ensuring signal integrity at frequencies where transmission line effects dominate.