layout-dependent effects (lde)

**Layout-Dependent Effects (LDE)** are **systematic variations in transistor performance caused by the physical layout context** — where the nearby structures (wells, STI, contacts, metal density) influence the stress, doping, and dimensions of the device, causing identical schematics to behave differently depending on layout. **What Are LDEs?** - **Types**: - **WPE** (Well Proximity Effect): Dopant scatter from well edge affects $V_t$. - **LOD** (Length of Diffusion): OD (active area) length affects stress. - **STI Stress**: Compressive stress from STI edges changes carrier mobility. - **PSE** (Poly Spacing Effect): Gate pitch affects etch and lithography. - **Magnitude**: Can cause 5-15% $I_{on}$ and 30-50 mV $V_t$ variation. **Why It Matters** - **Analog Matching**: Two "identical" transistors in different layout environments can mismatch significantly. - **SPICE Modeling**: Foundry PDKs include LDE models (BSIM-CMG, PSP) that must be extracted from layout. - **Design Rules**: Designers must place matching-critical devices in identical layout environments. **Layout-Dependent Effects** are **the neighborhood effect for transistors** — where your surroundings define your performance, just like real estate.