LDO Dropout Voltage
# LDO Dropout Voltage
Every linear regulator needs some voltage headroom between its input and output to keep its internal pass device operating correctly — a low-dropout regulator is defined specifically by how little of that headroom it needs. Dropout voltage is that minimum: the smallest input-to-output voltage difference at which the LDO can still hold its output in regulation, and once the input drops below output-plus-dropout, the output simply falls and tracks the input down with it, because the pass device has run out of room to keep working.
The pass device's own operating region is what sets the dropout floor, and a PMOS pass transistor gets there with much less headroom than a traditional NPN emitter follower ever could. Older linear regulators used an NPN pass transistor in an emitter-follower configuration, which inherently needs at least one base-emitter diode drop plus margin between input and output just to keep the transistor in its active region — typically 1.5 to 2 volts of dropout, a real tax on efficiency when input and output voltages are already close together. Modern LDOs instead use a PMOS pass device operated in its linear (triode) region, which can be driven with far less input-to-output voltage — the PMOS simply needs to stay out of cutoff, not maintain a diode drop — pushing dropout down to a few hundred millivolts or less. That architecture change, not a smarter feedback loop, is what actually earns the "low-dropout" name.
Dropout voltage isn't a fixed number — it scales with load current, because the pass device's own on-resistance sets the voltage it drops at a given current. The PMOS pass device, operating as a voltage-controlled resistor in its linear region near full conduction, has some finite channel resistance, and the voltage dropped across that resistance scales directly with load current — so a datasheet's dropout specification is always quoted at a specific load current, and dropout at a lower current can be meaningfully smaller than the headline number while dropout under a heavier load is correspondingly larger. This is why battery-powered and automotive designs that need to keep regulating as deeply as possible into a discharging or sagging supply specifically select LDOs characterized at their actual expected load current, not just the lowest number on a datasheet's front page.
Dropout and quiescent current trade against efficiency and noise performance in ways that make LDO selection a real design decision, not a commodity part swap. A smaller dropout generally comes with a larger pass-device channel width to keep on-resistance low at the target current, which raises the device's own parasitic capacitance and can complicate loop stability; ultra-low-noise LDOs used ahead of sensitive analog front-ends or PLLs often accept somewhat higher dropout in exchange for a quieter reference and better power-supply rejection, since noise performance and absolute dropout minimization pull in different directions in the pass-device sizing tradeoff. Power-management IC suppliers like Texas Instruments and Analog Devices offer entire families spanning this tradeoff space — ultra-low-dropout parts optimized for battery headroom, and low-noise parts that spend some of that headroom back on cleaner output rails.
Flicker noise (555) and kT/C noise (950) both set fundamental limits on how quiet an analog circuit's own signal path can be. LDO dropout voltage sets a completely different kind of limit — not how quiet the signal is, but how much of the supply rail's own voltage is actually available to work with before the regulator simply gives up and starts passing input-rail noise straight through unregulated.