line edge roughness (ler)

Line Edge Roughness (LER) refers to the random, nanometer-scale variation along the edges of patterned features in semiconductor lithography. It is measured as the 3-sigma deviation of the edge position from a perfectly straight reference line, typically quantified using scanning electron microscopy (SEM) or atomic force microscopy (AFM). LER arises from multiple sources including the stochastic nature of photon absorption in photoresist (shot noise), the molecular structure and aggregation behavior of resist polymers, acid diffusion during chemically amplified resist processing, and mask edge effects. As feature dimensions have shrunk to the single-digit nanometer regime, LER has become a critical limiter of device performance because a roughness of even 2-3 nm represents a significant fraction of the total feature width at advanced nodes. LER directly impacts transistor electrical characteristics by causing threshold voltage variability, increased leakage current, and reduced drive current uniformity. In SRAM cells, LER-induced Vt variation can limit minimum operating voltage and reduce yield. The International Roadmap for Devices and Systems (IRDS) specifies increasingly stringent LER requirements, calling for sub-1.5 nm 3-sigma values at leading-edge nodes. Mitigation strategies include optimizing resist chemistry with smaller molecular weight polymers, using smoothing techniques during etch transfer, applying post-develop treatments, and exploring resist platforms specifically designed for EUV lithography where stochastic effects are more pronounced due to fewer photons per pixel. Advanced patterning techniques like directed self-assembly (DSA) can potentially achieve very low LER values through the thermodynamic self-smoothing properties of block copolymers. LER is closely related to but distinct from Line Width Roughness (LWR), and the two are often correlated but not identical in their impact on device variability.