Mesa Production 1958 Mesa Etch Exposed Junction Edge

# Mesa Etch at Volume: Where the Exposed Junction Edge Becomes Unavoidable

## 1. Why the Same Etch That Isolates a Device Also Opens It to the Air

This step etches through the base-collector and emitter-base junctions on every wafer in the boat, the same mesa etch this project documented in 1956, cutting away the silicon around each die to isolate one device from its neighbors — and the geometry that isolation requires leaves both junctions physically exposed at the mesa's sidewall, open to whatever is in the atmosphere around it, for every single device this line now produces. At the scale of one demonstration wafer in 1956, an exposed junction edge was a known imperfection, documented and managed one device at a time. At production volume, that same imperfection becomes the line's single largest source of field failures, because an exposed junction is a surface, and a surface accumulates charge and contamination at a rate that depends on how long it sits exposed and what it is exposed to:

$$I_{\text{surf}} \propto Q_{\text{ss}} \cdot (1 - e^{-t/\tau}), \qquad Q_{\text{ss}} = \int_0^{t_{\text{exposed}}} J_{\text{contam}}(t')\,dt'$$

where $I_{\text{surf}}$ is surface leakage current, $Q_{\text{ss}}$ the accumulated surface-state charge, $\tau$ a characteristic charging time constant, and $J_{\text{contam}}$ the rate at which contaminants arrive at the exposed surface — moisture, ionic residue, airborne particulates — which depends on everything this line does *after* the mesa etch and before the device is finally sealed. Every minute this exposed edge spends in an uncontrolled atmosphere between this step and final packaging adds to $Q_{\text{ss}}$, and nothing about the device itself can undo that accumulation once it has happened.

Leakage Accumulates With Every Minute of Exposure surface leakage current versus time the junction edge sits uncovered SURFACE LEAKAGE VERSUS EXPOSURE TIME time the mesa sidewall sits exposed → Isurf reliable limit sealed quickly, still safe left exposed too long, unreliable Isurf ∝ Qss·(1−e−t/τ) — the clock starts the instant this etch opens the junction to the air this is the problem every step from here to final sealing exists to race against

## 2. Real Diagram: A Clean Cut That Leaves an Open Wound

The cross-section this etch produces is mechanically identical to 1956's: a mesa standing above the substrate, both junctions visible at the sidewall. What is different at volume is the fate of that sidewall between this step and the hermetic seal still many steps away — hours or days in an uncontrolled environment, carried through resist strips, probing, dicing, and handling, each one a further opportunity for contamination to reach a surface this etch has just made permanently vulnerable.

The Same Mesa, a Longer Road to Being Sealed cross-section at the moment of etch, and the exposure window that follows it MESA CROSS-SECTION, JUST ETCHED both junctions exposed at the sidewall THE ROAD TO A HERMETIC SEAL mesa etch resist strip probe dice sealed every red step along this chain is another hour the exposed edge is unprotected the etch is unchanged from 1956; what changed is how long its consequence has to wait before it is contained

## 3. Why 1956 Could Tolerate What Volume Cannot

The 1956 series documented this exact etch at Step 9 of that process, and its article treated the exposed sidewall as a known, manageable detail — a single wafer moved quickly from etch to passivation to packaging, and the window of vulnerability stayed short enough to be acceptable for a demonstration device. This line moves hundreds of wafers through the same sequence of steps at once, and queueing, batching, and handling delays between stations stretch that same window from minutes to hours or days for some fraction of the product. The etch chemistry has not changed at all since 1956; what has changed is that volume has turned a short, manageable exposure into a long, statistically distributed one, where some devices sit exposed far longer than others purely as an artifact of where they happened to be in the queue.

Step 5 does not create a new defect; it takes a defect 1956 could absorb at the pace of one wafer and multiplies its exposure time by however long this line's own throughput makes a device wait before it can finally be sealed.

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