molybdenum interconnect
**Molybdenum Interconnects** are the **next-generation metal wiring material being developed to replace copper and tungsten at the tightest pitches in advanced semiconductor nodes** — offering a higher melting point (2623°C vs. Cu 1085°C), lower electron mean free path at nanometer dimensions, and potential elimination of the barrier/liner layers that consume an increasing fraction of wire cross-section at sub-20 nm pitches, making Mo a strong candidate for local interconnects (M1-M2) at the 2 nm node and beyond.
**Why Copper Is Struggling**
```
Copper wire at 28 nm pitch:
Total width: 14 nm
Barrier (TaN/Ta): 2 nm × 2 sides = 4 nm
Liner (Co/Ru): 1 nm × 2 sides = 2 nm
Actual Cu: 14 - 4 - 2 = 8 nm ← Only 57% of wire is copper!
Resistivity of bulk Cu: 1.7 µΩ·cm
Resistivity of 8 nm Cu wire: ~15-20 µΩ·cm (10× higher due to grain boundary
and surface scattering)
Copper needs barriers to prevent diffusion into silicon → at narrow pitch,
barriers consume most of the wire cross-section
```
**Why Molybdenum**
| Property | Cu | W | Mo | Ru |
|----------|----|----|----|----|
| Bulk ρ (µΩ·cm) | 1.7 | 5.3 | 5.3 | 7.1 |
| ρ at 10 nm width | ~15-20 | ~25-30 | ~12-15 | ~15-20 |
| Needs barrier | Yes (TaN/Ta) | Yes (TiN) | No (refractory) | Minimal |
| Electromigration | Moderate | Excellent | Excellent | Good |
| Etch / Patterning | Damascene (CMP) | CVD fill | CVD/ALD fill, subtractive | Both |
| Electron MFP (nm) | 39 | 19 | 14 | 6.6 |
- Electron mean free path (MFP): Lower MFP → less resistivity increase at small dimensions.
- Mo MFP (14 nm) < Cu MFP (39 nm) → Mo resistivity degrades less as wires shrink.
- Barrierless: Mo is refractory → does not diffuse into silicon → no barrier needed.
- At sub-20 nm pitch, Mo has LOWER effective resistance than Cu (despite higher bulk ρ).
**Mo vs. Cu Effective Resistivity**
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**Mo Deposition and Patterning**
| Process | Method | Details |
|---------|--------|--------|
| Mo CVD | MoCl₅ + H₂ at 400-500°C | Conformal fill, moderate resistivity |
| Mo ALD | MoF₆ + Si₂H₆ / MoCl₅ + H₂ | Atomic-level control, low temperature |
| Subtractive patterning | Deposit blanket Mo → etch pattern | Alternative to damascene |
| Damascene | Trench etch → Mo fill → CMP | Similar to Cu process flow |
**Integration Challenges**
| Challenge | Issue | Status |
|-----------|-------|--------|
| CVD quality | Mo films can have high carbon/oxygen impurity | Improving with precursor chemistry |
| CMP | Mo CMP less mature than Cu CMP | Active development |
| Adhesion | Mo adhesion to dielectrics | Seed/adhesion layer optimization |
| Resistivity | CVD Mo: ~10-15 µΩ·cm (vs. bulk 5.3) | Within acceptable range |
| Via resistance | Mo-to-Cu via interface | Hybrid metallization (Mo M1 + Cu upper) |
**Industry Adoption**
- Intel: Announced Mo for buried power rail at Intel 18A (1.8 nm class).
- TSMC: Evaluating Mo and Ru for M1-M2 interconnects at N2 and beyond.
- Samsung: Research on Mo integration for GAA nodes.
- imec: Extensive Mo/Ru benchmarking for sub-2 nm interconnects.
Molybdenum interconnects represent **the most significant metallization change since the copper revolution of the late 1990s** — as copper's advantages disappear at nanometer-scale wire dimensions due to resistivity scaling and barrier overhead, Mo's shorter electron mean free path and barrierless integration offer a path to continuing interconnect scaling at the 2 nm node and beyond, ensuring that the wiring inside chips can keep pace with ever-shrinking transistors.