more moore
**More Moore** is the **continuation of traditional transistor scaling along Moore's Law** — pursuing higher transistor density, faster switching speed, and lower per-transistor cost through dimensional shrinking of CMOS transistors, enabled by advances in lithography (EUV, high-NA EUV), new transistor architectures (FinFET → GAA → CFET), and new materials (high-k dielectrics, 2D channel materials), representing the "keep scaling" path of semiconductor technology evolution.
**What Is More Moore?**
- **Definition**: The technology development path that continues to scale transistor dimensions according to Moore's Law — doubling transistor density every 2-3 years through smaller gate lengths, tighter metal pitches, and innovative device architectures that maintain electrostatic control at nanometer dimensions.
- **Moore's Law**: Gordon Moore's 1965 observation that transistor density doubles approximately every two years — More Moore is the engineering effort to sustain this exponential trend despite approaching atomic-scale physical limits.
- **Scaling Vectors**: Gate length reduction (shorter channels for faster switching), metal pitch reduction (denser wiring), cell height reduction (more compact standard cells), and 3D transistor architectures (FinFET, GAA) that improve density without requiring proportional dimensional shrinking.
- **Economic Driver**: Each new node provides ~50% area reduction (lower cost per transistor), ~30% speed improvement, or ~50% power reduction — this PPA improvement is the economic engine that justifies the $10-30 billion cost of building a new-generation fab.
**Why More Moore Matters**
- **Logic Density**: More Moore scaling has increased logic density from ~1 MTr/mm² (130nm, 2001) to ~290 MTr/mm² (3nm, 2023) — a 290× improvement that enables today's billion-transistor processors, GPUs, and AI accelerators.
- **AI Compute**: AI training requires exponentially growing compute — More Moore scaling provides the transistor density needed to build larger, more capable AI accelerators (NVIDIA H100: 80 billion transistors on TSMC 4nm).
- **Mobile Efficiency**: Smartphone SoCs depend on More Moore for the power efficiency that enables all-day battery life — each node generation reduces dynamic power by ~30-50% at the same performance level.
- **Economic Sustainability**: The semiconductor industry's $600B+ annual revenue depends on continued scaling providing enough value to justify the increasing cost of each new technology node.
**More Moore Scaling Roadmap**
- **FinFET Era (2012-2025)**: 3D fin-shaped channels replaced planar transistors at 22nm (Intel) / 16nm (TSMC), providing superior electrostatic control that enabled scaling from 22nm to 3nm.
- **GAA Nanosheet Era (2025-2028)**: Gate-all-around transistors with stacked nanosheet channels replace FinFETs at the 2nm node — the gate wraps all four sides of the channel for maximum electrostatic control.
- **CFET Era (2028-2032)**: Complementary FET stacks NMOS on top of PMOS in a single transistor footprint — approximately doubling density without requiring smaller feature sizes.
- **2D Materials Era (2030+)**: Atomically thin channel materials (MoS₂, WS₂) enable continued scaling when silicon channels become too thin to conduct effectively — the ultimate More Moore frontier.
| Node | Year | Architecture | Density (MTr/mm²) | Key Enabler |
|------|------|-------------|-------------------|-------------|
| 7nm | 2018 | FinFET | 91 | EUV (limited) |
| 5nm | 2020 | FinFET | 173 | Full EUV |
| 3nm | 2023 | FinFET | 292 | EUV multi-patterning |
| 2nm | 2025 | GAA Nanosheet | ~350 | GAA + BSPDN |
| 1.4nm | 2027 | GAA Optimized | ~450 | High-NA EUV |
| 1nm | 2029 | CFET | ~700 | CFET stacking |
**More Moore is the relentless pursuit of transistor scaling that has driven 60 years of semiconductor progress** — continuing to push dimensional limits through new transistor architectures, advanced lithography, and novel materials to deliver the density, performance, and efficiency improvements that power the digital economy.