MOSFET

A MOSFET, short for metal-oxide-semiconductor field-effect transistor, is a four-terminal device — source, drain, gate, and body — that controls current flow between its source and drain terminals using an electric field from the gate, with a thin insulating oxide layer physically separating the gate from the channel it controls so that essentially no current flows into the gate terminal itself. That gate-current-free control is the defining trait that separates a MOSFET from an older transistor family, the bipolar junction transistor, which instead needs a continuous base current to stay on — a difference with real consequences for power consumption, switching speed, and how each device gets used. How a MOSFET actually forms and controls its conducting channel looks like this:

A few things are worth knowing about why a MOSFET's gate-oxide isolation matters so much, and why real MOSFETs come in genuinely different flavors for genuinely different jobs:

A MOSFET needing essentially zero steady-state gate current, because the gate is capacitively coupled through an insulating oxide rather than directly connected to the channel, is the single biggest reason MOSFETs displaced bipolar transistors as the dominant device in digital logic. A bipolar junction transistor needs continuous base current flowing the entire time it's held on, which means a circuit built from bipolar transistors burns power just holding a logic state steady, not only while switching. A MOSFET's gate draws current only briefly, while charging or discharging the small gate capacitance during a switching transition — once the gate voltage settles at a steady value, the current into the gate drops to a vanishingly small leakage level, meaning a MOSFET holding a steady logic state consumes almost no power at all. This is precisely why CMOS logic, built from paired MOSFETs, became the dominant technology for digital chips: billions of transistors can sit in a fixed logic state simultaneously while the chip as a whole still consumes comparatively little static power, something equivalent bipolar circuitry could never achieve at that scale.

NMOS and PMOS are mirror-image MOSFET types built with opposite carrier polarities, and pairing them together is precisely the mechanism that makes CMOS logic's near-zero static power consumption possible. An NMOS device uses n-type source and drain regions in a p-type body, conducts via electrons, and turns on when its gate voltage is pulled high relative to its source; a PMOS device uses the opposite doping arrangement, conducts via holes, and turns on when its gate voltage is pulled low relative to its source. Wiring one NMOS and one PMOS transistor together so their gates share a common input means that for any given input voltage, exactly one of the two conducts while the other stays off — there's essentially never a direct, continuous current path from supply to ground through the pair, which is the structural reason CMOS logic burns power almost exclusively while actively switching rather than while holding a steady state.

Enhancement-mode and depletion-mode MOSFETs differ in whether a channel exists by default at zero gate voltage, and that single distinction determines whether a device is normally off or normally on, which matters enormously for circuit safety. An enhancement-mode MOSFET, by far the dominant type in digital logic, has no conducting channel at zero gate bias — it needs a gate voltage past its threshold to create one, meaning the device is normally off and only conducts when deliberately turned on. A depletion-mode MOSFET is built with a channel already present at zero gate bias, conducting by default until a gate voltage is applied to deplete that channel and turn the device off — a normally-on behavior useful in specific niche applications but generally considered less safe as a default in power switching, since a circuit fault that accidentally removes gate control leaves a depletion-mode device stuck conducting rather than stuck safely off.

Power MOSFETs, used for switching large currents in power supplies and motor drives rather than the microscopic switching inside a logic chip, are built with a fundamentally different vertical structure specifically to handle much higher voltage and current than a planar logic transistor ever needs to. Instead of a flat, planar structure like the MOSFETs packed by the billions onto a digital chip, a power MOSFET typically uses a vertical architecture where current flows from the top surface down through the device to the bottom, allowing the drain contact to cover the entire chip's backside and dramatically lowering the device's on-resistance for a given die area. On-resistance — how much the device resists current flow while fully switched on — is the headline specification for a power MOSFET precisely because that resistance times the current squared determines how much power the device wastes as heat while conducting, directly setting the efficiency ceiling for whatever power converter or motor driver the device sits inside.

Read a MOSFET through its gate-oxide isolation, not just its switch function: that physical separation between gate and channel is what lets it hold a logic state with almost no standing current, NMOS and PMOS pairing is what turns that property into CMOS logic's power efficiency at chip scale, and the same basic structure — reshaped vertically and optimized for on-resistance rather than switching speed — becomes an entirely different-looking device once the job shifts from logic switching to power conversion.