MOSFET 1962 Deposit Pattern Metal Gate Electrode

# Deposit and Pattern the Metal Gate Electrode Over the Channel: A Margin That Must Exist, and a Cost for Every Bit of It

## 1. Why the Gate Must Be Wider Than the Channel It Controls

This step evaporates a layer of aluminum over the finished oxide and patterns it, using the same photolithographic technique this project established in 1957, into the gate electrode that must sit directly above the channel Step 3 left between the two diffused regions — but because this mask, like every mask before it in this project's history, can only be aligned to the wafer beneath it within some finite tolerance, the gate cannot simply be drawn to match the channel's own width exactly. If the gate were drawn to land precisely at the channel's edges and the mask then landed even slightly off that intended position, a thin strip of channel would be left completely uncovered by the gate — and an uncovered strip of channel cannot be inverted by any gate voltage at all, leaving the device unable to conduct regardless of bias, a failure with no graceful degradation. The gate must therefore be drawn deliberately wider than the channel, overlapping onto each diffused region by a margin large enough to guarantee full coverage under the worst alignment error this process can produce.

$$C_{\text{overlap}} = \frac{\epsilon_{\text{ox}}}{t_{\text{ox}}}\,W\,L_{\text{overlap}}, \qquad L_{\text{overlap}} \geq \Delta_{\text{align}}$$

where $L_{\text{overlap}}$ is the gate's deliberate extension past the channel edge onto each diffused region, $\Delta_{\text{align}}$ the worst-case mask misalignment this process must tolerate, $W$ the gate width, and $C_{\text{overlap}}$ the resulting parasitic capacitance formed wherever the gate sits directly above a diffused region instead of above the channel — every bit of overlap margin large enough to guarantee the device will turn on at all also adds a capacitance that did not exist in the idealized structure, a cost this step cannot avoid paying, because the alternative to paying it is a device that sometimes does not work.

Too Little Margin Fails Outright; Enough Margin Costs Capacitance the same misalignment, two different consequences depending on the drawn overlap GATE DRAWN TO MATCH CHANNEL EXACTLY exposed misalignment leaves a strip ungated device cannot conduct at all GATE DRAWN WITH DELIBERATE OVERLAP channel stays fully covered despite the same misalignment but the overlap itself now forms Coverlap Loverlap ≥ Δalign — the margin is not optional, only its cost is this device trades a guaranteed function for a parasitic this project has never had to pay before

## 2. Real Diagram: The Gate, Deliberately Wider, and the Capacitance That Overlap Creates

The cross-section below shows the finished gate electrode after patterning, extending past the channel's own edges onto both diffused regions, with the resulting overlap capacitance annotated directly on each side where the gate now sits above diffused silicon rather than above the channel it was meant to control.

The Gate, Wider Than the Channel, by Design the overlap on each side is deliberate margin, not a fabrication error metal gate electrode Coverlap Coverlap channel, now guaranteed fully covered by the gate above it no self-aligned gate process exists yet — this overlap is how alignment tolerance is paid for

## 3. The First Alignment Tolerance This Project Has Ever Had to Pay For With a Parasitic

Every photolithographic step this project has used since 1957 has carried some alignment tolerance, and every earlier series managed that tolerance by accepting a probability of yield loss when a mask landed too far off target — a misaligned window in a bipolar process typically meant a device built slightly off-spec, not a device that failed to function at all. This step is different in kind. Because an uncovered strip of channel simply cannot conduct no matter what gate voltage is applied, there is no acceptable degree of misalignment this gate can risk; the overlap margin is not a yield optimization, it is a hard requirement for the device to function as a transistor at all. Paying for that requirement, in the complete absence of any technique to align the gate to the diffused regions automatically, means deliberately sacrificing part of the gate's own area to a capacitance this project has never had to budget for before — not a junction capacitance arising from a doping profile, but a parasitic created directly by the margin a mask-alignment tolerance forces a designer to draw.

Step 4 does not simply add a gate electrode to the structure Step 3 built; it pays, in parasitic capacitance, for the one thing every earlier masking step in this project could risk losing and this one cannot: the guarantee that the device underneath actually works.

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