multi-die chiplet design
**Multi-Die Chiplet Design Methodology** is the **chip architecture approach that disaggregates a monolithic SoC into multiple smaller silicon dies (chiplets) connected through high-bandwidth die-to-die interconnects on an advanced package — enabling mix-and-match of different process nodes, higher aggregate yields, IP reuse across products, and economically viable scaling beyond the reticle limit of a single lithography exposure**.
**Why Chiplets Replaced Monolithic**
Monolithic dies face three walls simultaneously: the reticle limit (~858 mm² maximum die size for a single EUV exposure), the yield wall (defect density × die area = exponentially decreasing yield for large dies), and the economics wall (leading-edge process cost per mm² doubles every 2-3 years). A 600 mm² monolithic die at 3 nm might yield 30-40%; splitting it into four 150 mm² chiplets yields 70-80% each, with overall good-die yield dramatically higher.
**Die-to-Die Interconnect Standards**
- **UCIe (Universal Chiplet Interconnect Express)**: Industry standard (Intel, AMD, ARM, TSMC, Samsung). Defines physical layer (bump pitch, PHY), protocol layer (PCIe, CXL), and software stack. Standard reach: 2 mm (on-package), 25 mm (off-package). Bandwidth density: 28-224 Gbps/mm at the package edge.
- **BoW (Bunch of Wires)**: OCP-backed open standard for low-latency, energy-efficient D2D links. Parallel signaling with minimal SerDes overhead — targeting <0.5 pJ/bit.
- **Proprietary**: AMD Infinity Fabric (EPYC/MI300), Intel EMIB/Foveros, NVIDIA NVLink-C2C (Grace Hopper). Often higher bandwidth than open standards but lock-in risk.
**Chiplet Architecture Design Decisions**
- **Functional Partitioning**: Which functions go on which chiplets? Compute cores on leading-edge node (3 nm), I/O and analog on mature node (12-16 nm), memory controllers near HBM stacks. Partitioning minimizes leading-edge silicon area while maximizing performance.
- **Interconnect Bandwidth Budgeting**: The D2D link bandwidth must match the data flow between chiplets. A cache-coherent fabric requires 100+ GB/s per link; a PCIe-style I/O link needs 32-64 GB/s. Under-provisioning creates a performance cliff.
- **Thermal Co-Design**: Multiple chiplets on one package create hotspot interactions. Thermal simulation must account for inter-chiplet heat coupling and package-level thermal resistance.
- **Test Strategy**: Each chiplet is tested as a Known Good Die (KGD) before assembly. D2D interconnect is tested post-bonding with BIST circuits embedded in the PHY.
**Industry Examples**
| Product | Chiplets | Process Mix | Package |
|---------|----------|-------------|---------|
| AMD EPYC Genoa | 12 CCD + 1 IOD | 5nm + 6nm | Organic substrate |
| Intel Meteor Lake | 4 tiles | Intel 4 + TSMC N5/N6 | Foveros + EMIB |
| NVIDIA Grace Hopper | GPU + CPU | TSMC 4N + 4N | CoWoS-L C2C |
| Apple M2 Ultra | 2× M2 Max | TSMC N5 | UltraFusion |
Multi-Die Chiplet Design is **the architectural paradigm that sustains Moore's Law economics beyond the limits of monolithic scaling** — enabling semiconductor companies to build systems larger, more capable, and more economically than any single die could achieve.