multi voltage floorplan
**Multi-Voltage Floor Planning** is the **physical design strategy of partitioning the chip layout into distinct voltage regions (voltage islands) with properly managed boundaries** — ensuring that each power domain has dedicated supply routing, level shifters at every signal crossing between voltage domains, and isolation cells at boundaries to power-gated domains, while optimizing area, wirelength, and power delivery across 5-20+ voltage domains that characterize modern mobile and server SoCs.
**Why Multi-Voltage**
- Different blocks have different performance requirements:
- CPU cores: 0.65-1.1V (DVFS range).
- GPU: 0.7-0.9V.
- Always-on logic: 0.75V (fixed).
- I/O: 1.2V or 1.8V or 3.3V.
- SRAM: May need slightly higher voltage for stability.
- Running everything at highest voltage wastes 2-4× power.
**Voltage Domain Types**
| Domain Type | Characteristics | Example |
|-------------|----------------|---------|
| Always-on | Never powered off, fixed voltage | PMU, clock gen, interrupt controller |
| DVFS | Variable voltage/frequency | CPU cores, GPU |
| Switchable | Can be completely powered off | Modem, camera ISP (when unused) |
| Retention | Powered off but state preserved | CPU during deep sleep |
| I/O | Fixed voltage matching external standard | DDR PHY (1.1V), GPIO (1.8V) |
**Floorplan Requirements**
- **Domain contiguity**: Each voltage domain should be a contiguous region (simplifies power routing).
- **Level shifter placement**: At every signal crossing between different voltage domains.
- High-to-low: Simple buffer (can also just work in some cases).
- Low-to-high: Requires dedicated level shifter cell.
- **Isolation cell placement**: At outputs of switchable domains → clamp to safe value when off.
- **Power switch placement**: Header (PMOS) or footer (NMOS) switches distributed across switchable domains.
**Power Grid Design Per Domain**
- Each domain needs its own VDD supply mesh.
- VSS (ground) typically shared across all domains.
- Power switches connect always-on VDD to switched VDD nets.
- Grid density proportional to domain current demand.
- Multiple metal layers for power: Typically M8-M10 for global, M1-M3 for local.
**Level Shifter Strategy**
| Crossing | From | To | Shifter Type |
|----------|------|----|--------------|
| Signal: Low → High | 0.7V domain | 1.0V domain | Full-swing level shifter |
| Signal: High → Low | 1.0V domain | 0.7V domain | Simple buffer or dedicated |
| Enable: AO → Switchable | Always-on | Switched domain | Isolation-aware |
| Clock: AO → Any | Clock domain | Target | Special low-jitter shifter |
**Physical Design Challenges**
- **Domain boundary routing**: Level shifters and isolation cells add congestion at boundaries.
- **Timing impact**: Level shifters add 50-200 ps delay → affects timing budgets.
- **Power grid IR drop**: Each domain must independently meet IR drop targets.
- **Well tie rules**: Each domain needs proper N-well and P-well ties to correct supply.
- **Fill and density**: Metal density rules must be met within each domain independently.
Multi-voltage floor planning is **the physical manifestation of the chip's power architecture** — getting it right determines whether the aggressive power management strategies encoded in UPF specifications can actually be implemented in silicon, with mistakes in voltage domain boundary management causing functional failures that are extremely difficult to debug post-silicon.