nanosheet fet
**Gate-All-Around (GAA) nanosheet transistor** is the device architecture that succeeds FinFET at the 3 nm node and below — a stack of horizontal silicon nanosheets where the gate electrode wraps all four sides of each channel, delivering the tightest electrostatic control physically possible in a planar-compatible flow. TSMC calls it N2 (2025), Intel calls it RibbonFET / Intel 20A (2024), and Samsung calls it 3GAE / MBCFET (2022 risk). The architecture solves FinFET's fundamental scaling wall: once the fin is too narrow to conduct useful current, the only path forward is stacking multiple wider sheets and gating them from every direction.
**Why FinFET ran out of road.** A FinFET gates three sides of a tall, narrow fin. As gate length shrinks below ~12 nm, the fin must get narrower to maintain short-channel control — but carrier mobility in a sub-5 nm fin collapses due to surface roughness and quantum confinement. GAA sidesteps this by using wider sheets (30–50 nm) that are thin vertically (5–7 nm) and fully surrounded — electrostatic control improves while drive current scales with sheet width × number of stacked sheets.
**Electrostatic advantage — the natural length.** The quality of gate control is captured by the natural length $\lambda$. For a rectangular nanosheet gated on all four sides:
$$\lambda_{\text{GAA}} = \sqrt{\frac{\varepsilon_{\text{si}}}{\varepsilon_{\text{ox}}} \cdot \frac{t_{\text{si}} \cdot t_{\text{ox}}}{4}}$$
Compare FinFET (three-sided gate):
$$\lambda_{\text{FinFET}} = \sqrt{\frac{\varepsilon_{\text{si}}}{\varepsilon_{\text{ox}}} \cdot \frac{t_{\text{si}} \cdot t_{\text{ox}}}{3}}$$
The factor of 4 vs 3 in the denominator gives GAA a ~15 % shorter natural length at the same body thickness — which directly translates to less DIBL, steeper subthreshold swing, and lower leakage at matched gate length.
**The nanosheet stack — a superlattice epitaxy.** Fabrication begins with alternating epitaxial Si/SiGe layers grown on the substrate: 3–4 pairs of SiGe₀.₃ sacrificial layers (5–8 nm) interleaved with Si channel layers (5–7 nm). Total stack height: 40–60 nm. Thickness uniformity must hold to <0.1 nm across the wafer because any variation propagates into threshold-voltage mismatch across billions of transistors.
**Inner spacer — the module that didn't exist in FinFET.** After dummy-gate patterning and source/drain cavity etch, the SiGe sacrificial layers are selectively recessed laterally (2–5 nm pullback) with a vapor-phase HCl or dry isotropic etch. Low-k dielectric (SiOCN or SiCO, $k \approx$ 4–5) fills the cavities and is etched back, leaving inner spacers that isolate the gate from the source/drain epitaxy. These spacers define the parasitic gate-to-S/D capacitance — the single largest contributor to AC performance loss at advanced nodes.
**Channel release — the defining GAA etch.** After removing the dummy gate, a highly selective isotropic etch removes the SiGe sacrificial layers while leaving the Si nanosheets intact. Selectivity requirement: >100:1 (SiGe:Si). The released sheets are then cleaned and prepared for high-k/metal-gate (HKMG) deposition, which wraps conformally around all four sides of each sheet.
**Drive-current scaling — width × stacks.** Unlike FinFET where current scales only by adding more fins (at a fixed narrow width), GAA lets designers tune two independent knobs:
| Parameter | FinFET (5 nm) | GAA nanosheet (3 nm) | GAA nanosheet (2 nm) |
|---|---|---|---|
| Channel shape | Tall narrow fin, 5–7 nm wide | Horizontal sheet, 30–50 nm wide | Sheet, 30–50 nm wide |
| Gate coverage | 3 sides | 4 sides (all-around) | 4 sides |
| Stacked channels | 1 fin = 1 channel (height ≈ 50 nm) | 3–4 stacked sheets | 4–5 stacked sheets |
| Drive current per track | Limited by fin pitch | Sheet width × N_sheets | Sheet width × N_sheets |
| $V_{\text{th}}$ tuning | Fin doping (limited) | Work-function metal + sheet thickness | WFM + sheet thickness |
| DIBL (mV/V) | 30–50 | 15–30 | 10–25 |
| SS (mV/dec) | 65–75 | 62–68 | 60–65 |
| Contacted poly pitch (CPP) | 48–51 nm | 45–48 nm | 42–45 nm |
| Metal pitch (Mx) | 24–28 nm | 21–24 nm | 18–21 nm |
**Backside power delivery (BSPDN).** At 2 nm and below, the metal interconnect stack above the transistors is so dense that routing power rails on the frontside wastes ~20 % of the standard-cell area. GAA at N2/20A pairs with backside power delivery — power (VDD/VSS) rails are fabricated on the wafer backside after wafer thinning, connected to the transistors through nano-TSVs. This recovers routing tracks for signals and shrinks cell height by 1–2 tracks.
**Thermal and reliability.** Stacking 3–4 channels inside a ~60 nm pillar concentrates heat. Self-heating in the inner sheets (farther from the substrate heat sink) is 10–30% worse than FinFET at the same power density. Mitigation: thinner SiGe (wider thermal path between sheets after release), metal gate fill optimization, and backside cooling pathways through the nano-TSVs. Reliability shifts from fin-corner TDDB (FinFET) to sheet-edge gate-oxide stress — the tight inner curvature concentrates the electric field.
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**Process complexity and cost.** GAA adds ~15–20 % more mask layers than FinFET at the same node: inner spacer etch/dep, selective SiGe release, multi-threshold work-function-metal patterning inside the tight gate-all-around cavity, and (at N2) backside lithography. Wafer cost at N2 is estimated at $25,000–$30,000 per 300 mm wafer (vs $16,000–$20,000 for N3 FinFET) — a cost that only AI-accelerator and high-end SoC volumes can absorb.
**The road ahead — CFET.** Beyond 4–5 stacked sheets, the next architectural step is CFET (complementary FET): the NMOS nanosheet stack is placed directly above (or below) the PMOS stack within the same standard-cell footprint, cutting cell area roughly in half. CFET is projected for the Å-scale nodes (TSMC A14, Intel 14A, ~2028–2030) and requires sequential or monolithic 3D integration — bonding or growing two active device layers with aligned contacts between them.