Nanosheet Transistor Fabrication

# Nanosheet Transistor Fabrication: Unit Process Integration & Physics

Nanosheet transistor fabrication is the primary semiconductor manufacturing methodology for leading-edge logic devices at the 3 nm, 2 nm, and sub-2 nm (A16 / A14) nodes, replacing conventional three-dimensional FinFETs. Marketed under foundry designations such as Gate-All-Around (GAA), Multi-Bridge Channel FET (MBCFET), and RibbonFET, the nanosheet architecture wraps a replacement High-k Metal Gate (HKMG) around all four sides of multiple vertically stacked, atomically thin silicon channel ribbons ( $T_{ns} \approx 5\,\text{nm}$ , $W_{ns} \approx 15\text{ to }55\,\text{nm}$ ).

Compared to FinFETs—which are constrained by discrete, quantized fin counts ( $N_{fin} \in \{1, 2, 3\}$ )—nanosheets provide continuous, lithographically adjustable channel widths ( $W_{ns}$ ), enabling circuit designers to fine-tune the drive current ( $I_{on}$ ) and parasitic capacitance ( $C_{gg}$ ) within standard logic cells without altering the standard cell height. However, realizing this 3D architecture introduces formidable unit process challenges: heteroepitaxial growth of defect-free multi-layer $\text{Si} / \text{Si}_{1-x}\text{Ge}_x$ superlattices, cryogenic high-aspect-ratio fin etching, atomic-precision inner spacer cavity recess, and selective vapor-phase channel release etching with zero silicon loss.

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## 1. Multi-Layer Superlattice Epitaxy Physics & Strain Control

The manufacturing sequence initiates with the heteroepitaxial growth of alternating single-crystal silicon ( $\text{Si}$ ) and silicon-germanium ( $\text{Si}_{1-x}\text{Ge}_x$ ) layers on a $300\,\text{mm}$ $\text{Si}(001)$ substrate via Reduced-Pressure Chemical Vapor Deposition (RP-CVD) using dichlorosilane ( $\text{SiH}_2\text{Cl}_2$ ) and germane ( $\text{GeH}_4$ ) precursors:

\text{SiH}_2\text{Cl}_2(g) \to \text{Si}(s) + 2\text{HCl}(g)

\text{GeH}_4(g) \to \text{Ge}(s) + 2\text{H}_2(g)

### 1.1 Misfit Strain & Matthews-Blakeslee Critical Thickness
Because the lattice constant of germanium ( $a_{\text{Ge}} = 5.657\,\text{Å}$ ) is larger than that of silicon ( $a_{\text{Si}} = 5.431\,\text{Å}$ ), the $\text{Si}_{1-x}\text{Ge}_x$ layers grow under pseudomorphic biaxial compressive strain. The lattice mismatch strain $$f$$ is given by:

f = \frac{a_{\text{SiGe}} - a_{\text{Si}}}{a_{\text{Si}}} \approx 0.042 \cdot x_{\text{Ge}}

For a typical germanium mole fraction of $x_{\text{Ge}} = 0.30$ ( $30\%\,\text{Ge}$ ):

f \approx 0.042 \cdot 0.30 \approx 0.0126\text{ (1.26% compressive strain)}

To prevent plastic strain relaxation via the generation of misfit and threading dislocations ( $D_{threading} < 10^3\,\text{cm}^{-2}$ ), the thickness of each individual $\text{SiGe}$ layer ( $t_{sac} \approx 10\text{ to }12\,\text{nm}$ ) and the total cumulative thickness of the superlattice must remain strictly below the Matthews-Blakeslee equilibrium critical thickness ( $$h_c$$ ):

h_c = \frac{b (1 - \nu \cos^2 \alpha)}{8 \pi (1 + \nu) f \cos \lambda} \left[ \ln\left( \frac{h_c}{b} \right) + 1 \right]

Where:
- $b = \frac{a_{\text{Si}}}{\sqrt{2}} \approx 3.84\,\text{Å}$ is the Burgers vector of a $60^\circ$ dislocation.
- $\nu \approx 0.28$ is Poisson's ratio for silicon.
- $\alpha = 60^\circ$ and $\lambda = 60^\circ$ are the characteristic slip geometry angles for the diamond cubic lattice.

Maintaining the superlattice below $$h_c$$ ensures atomically sharp, defect-free hetero-interfaces ( $\Delta \sigma_{interface} < 0.3\,\text{nm}$ ), preventing source-to-drain leakage paths and junction degradation.

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## 2. Quantitative Modeling: Width Tuning & Electrostatic Scaling

### 2.1 Effective Channel Width Formulation
In a FinFET, the effective conduction channel width $W_{eff}$ is constrained to discrete multiples of the fin height ( $H_{fin}$ ) and fin width ( $W_{fin}$ ):

W_{eff,FinFET} = N_{fin} \cdot (2 H_{fin} + W_{fin})

Because $N_{fin}$ can only take integer values ( $$1, 2, 3$$ ), standard cell layout requires wide drive-strength steps ( $1\times, 2\times, 3\times$ ). If a logic path requires $1.3\times$ drive current, the designer is forced to instantiate a $2\times$ fin cell, burning unnecessary dynamic power ( $P_{dyn} = \alpha C V_{DD}^2 f$ ) and silicon area.

In contrast, the GAA nanosheet effective channel width wraps around all four boundaries of $N_{sheets}$ stacked ribbons:

W_{eff,GAA} = N_{sheets} \cdot (2 W_{ns} + 2 T_{ns})

Where $W_{ns}$ is continuously variable in mask layout ( $15\,\text{nm} \le W_{ns} \le 55\,\text{nm}$ ) and $T_{ns} \approx 5\,\text{nm}$ . For a 3-nanosheet stack:
- At minimum width ( $W_{ns} = 15\,\text{nm}$ ):

W_{eff} = 3 \cdot \big( (2 \cdot 15) + (2 \cdot 5) \big) = 3 \cdot 40 = 120\,\text{nm}

At high-drive width ( $W_{ns} = 50\,\text{nm}$ ):

W_{eff} = 3 \cdot \big( (2 \cdot 50) + (2 \cdot 5) \big) = 3 \cdot 110 = 330\,\text{nm}

Circuit designers can continuously scale $W_{eff}$ by $+10\%$ or $+20\%$ to satisfy setup-time timing closure without incurring discrete fin pitch layout penalties.

### 2.2 Electrostatic Gate Control & Natural Scaling Length
The superior short-channel effect (SCE) immunity of Gate-All-Around nanosheets is quantified by the natural scaling length ( $\lambda_{GAA}$ ):

\lambda_{GAA} = \sqrt{\frac{\epsilon_{Si}}{4 \epsilon_{ox}} T_{ns} t_{ox} \left( 1 + \frac{T_{ns}}{W_{ns}} \right)^{-1}}

Where:
- $\epsilon_{Si} = 11.7$ and $\epsilon_{ox} = 3.9$ are the relative dielectric permittivities.
- $T_{ns} \approx 5\,\text{nm}$ is the nanosheet channel thickness.
- $t_{ox} \approx 1.2\,\text{nm}$ is the Equivalent Oxide Thickness (EOT).
- $W_{ns} \approx 30\,\text{nm}$ is the nanosheet width.

Calculating $\lambda_{GAA}$ :

\lambda_{GAA} \approx \sqrt{\frac{11.7}{4 \cdot 3.9} \cdot (5 \times 10^{-9}) \cdot (1.2 \times 10^{-9}) \cdot \left( 1 + \frac{5}{30} \right)^{-1}} \approx \sqrt{0.75 \cdot 6 \times 10^{-18} \cdot 0.857} \approx 1.96\,\text{nm}

To suppress short-channel effects, the gate length must satisfy $L_g \ge 4.5 \cdot \lambda_{GAA} \approx 8.8\,\text{nm}$ . This ensures subthreshold swing remains near the physical room-temperature limit:

\text{SS} = \frac{k_B T}{q} \ln(10) \left( 1 + \frac{C_d}{C_{ox}} \right) \approx 64\,\text{mV/dec}

And suppresses Drain-Induced Barrier Lowering to $\text{DIBL} < 40\,\text{mV/V}$ at $L_g = 12\,\text{nm}$ .

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## 3. Critical Release Etch Chemistry: Vapor HCl vs. Plasma Fluorination

The replacement metal gate (RMG) process requires removing the sacrificial $\text{Si}_{1-x}\text{Ge}_x$ layers to suspend the crystalline silicon nanosheets. This step is among the highest-risk modules in semiconductor manufacturing.

+----------------------------------------------------------------------------------------------------+
|                               NANOSHEET RELEASE ETCH CHEMISTRY COMPARISON                          |
+----------------------+-------------------------------------+---------------------------------------+
| METRIC               | THERMAL VAPOR-PHASE HCl             | DOWNSTREAM ISOTROPIC PLASMA (NF₃/O₂)  |
+----------------------+-------------------------------------+---------------------------------------+
| Chemical Reaction    | SiGe + HCl -> SiH₂Cl₂ + GeCl₄↑      | SiGe + F* -> SiF₄↑ + GeF₄↑            |
+----------------------+-------------------------------------+---------------------------------------+
| Process Window Temp  | 550°C to 650°C (Reduced pressure)   | 0°C to 50°C (Cryogenic or near-ambient)|
+----------------------+-------------------------------------+---------------------------------------+
| Selectivity SiGe:Si  | > 250:1 (Near-zero silicon attack)  | ~ 100:1 to 150:1                      |
+----------------------+-------------------------------------+---------------------------------------+
| Silicon Surface      | Atomically smooth (100) facets;     | Moderate surface roughness; risk of   |
| Roughness (RMS)      | RMS < 0.15 nm                       | radical bombardment (RMS ~ 0.35 nm)   |
+----------------------+-------------------------------------+---------------------------------------+
| Stiction / Capillary | Zero (Gas-phase dry sublimation;    | Zero (Gas-phase dry sublimation)      |
| Collapse Risk        | no liquid capillary meniscus)       |                                       |
+----------------------+-------------------------------------+---------------------------------------+
| Inner Spacer Attack  | Negligible on SiBCN / SiOCN         | Low, but requires tight F* flux control|
+----------------------+-------------------------------------+---------------------------------------+
| High-Volume Status   | Standard in TSMC N2, Samsung SF3    | Alternative / complementary clean     |
+----------------------+-------------------------------------+---------------------------------------+

### 3.1 Nanosheet Stiction & Capillary Collapse Prevention
In wet chemical etching, liquid surface tension during rinse and dry steps produces capillary forces between adjacent nanosheets:

P_{capillary} = \frac{2 \gamma \cos \theta}{d_{gap}}

Where $\gamma \approx 72.8\,\text{mN/m}$ is the surface tension of water, $\theta$ is the contact angle, and $d_{gap} \approx 10\,\text{nm}$ is the inter-sheet separation. This generates an attractive pressure exceeding:

P_{capillary} \approx \frac{2 \cdot 0.0728}{10 \times 10^{-9}} \approx 14.5\,\text{MPa}

This force easily bends the ultra-thin $5\,\text{nm}$ silicon ribbons, causing irreversible mechanical stiction and permanent short circuits. High-volume manufacturing completely eliminates this defect mode by deploying purely gas-phase thermal vapor $\text{HCl}$ etching in an integrated cluster tool under continuous vacuum.

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## 4. Replacement High-k Metal Gate (HKMG) Integration

Once the silicon nanosheets are suspended, the functional gate stack must be conformally deposited into the sub-10 nm cavities surrounding each sheet:
1. Chemical Interface Oxide ( $\text{SiO}_x$ ): Ozone-based or remote plasma oxidation forms a high-purity $0.6\text{ to }0.8\,\text{nm}$ interfacial $\text{SiO}_2$ layer with minimal interface trap density ( $D_{it} < 10^{11}\,\text{eV}^{-1}\text{cm}^{-2}$ ).
2. High-k Dielectric Layer ( $\text{HfO}_2$ ): Atomic Layer Deposition (ALD) of hafnium dioxide ( $\kappa \approx 20\text{ to }25$ ) using tetrakis(dimethylamido)hafnium (TDMAH) and $\text{H}_2\text{O}$ or $\text{O}_3$ , targeting an Equivalent Oxide Thickness of $\text{EOT} \approx 0.8\text{ to }1.0\,\text{nm}$ .
3. Multi-Threshold Voltage ( $$V_t$$ ) Workfunction Metals (WFM):
- NMOS: Ultrathin layers of $\text{TiAl}$ , $\text{TiAlC}$ , or $\text{TaAlC}$ deposited via ALD to position the effective workfunction near the conduction band ( $\Phi_{eff} \approx 4.1\text{ to }4.3\,\text{eV}$ ).
- PMOS: Dense, nitrogen-rich $\text{TiN}$ or $\text{TaN}$ layers to position the workfunction near the valence band ( $\Phi_{eff} \approx 4.9\text{ to }5.1\,\text{eV}$ ).
4. Low-Resistance Core Fill: Chemical Vapor Deposition (CVD) or ALD of fluorine-free tungsten ( $\text{FFW}$ ) or ruthenium ( $\text{Ru}$ ) to backfill the remaining gate cavity without leaving internal seam voids.

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## 5. Technology Comparison: FinFET to Nanosheet Evolution

+----------------------------------------------------------------------------------------------------+
|                               COMPARATIVE MATRIX OF LOGIC CELL ARCHITECTURES                       |
+----------------------+---------------------+-----------------------+-------------------------------+
| METRIC               | 7nm / 5nm FINFET    | 3nm / 2nm GAA (N2)    | SUB-2nm CFET (A14 / A10)      |
+----------------------+---------------------+-----------------------+-------------------------------+
| Gate Topology        | 3-sided vertical    | 4-sided full wrap     | 4-sided full wrap             |
|                      | channel control     | around nanosheets     | (Vertically stacked N-over-P) |
+----------------------+---------------------+-----------------------+-------------------------------+
| Channel Geometry     | Fin Height: ~50 nm  | Sheet Width: 15–55 nm | Dual Sheet Stacks             |
|                      | Fin Width: 6–7 nm   | Sheet Thick: 5 nm     | Width: 25–40 nm, Thick: 5 nm  |
+----------------------+---------------------+-----------------------+-------------------------------+
| Channel Width Tuning | Quantized (Integer  | Continuous (Litho mask| Continuous (Independent       |
| Flexibility          | number of fins)     | sheet width variation)| N/P width tuning)             |
+----------------------+---------------------+-----------------------+-------------------------------+
| Subthreshold Swing   | 68 to 75 mV/dec     | 62 to 66 mV/dec       | 62 to 65 mV/dec               |
| (SS @ short Lg)      |                     | (Near ideal limit)    | (Near ideal limit)            |
+----------------------+---------------------+-----------------------+-------------------------------+
| DIBL Resistance      | 55 to 70 mV/V       | 35 to 45 mV/V         | < 40 mV/V                     |
+----------------------+---------------------+-----------------------+-------------------------------+
| Standard Cell Height | 6.0T to 7.5T        | 4.5T to 5.0T          | 3.0T to 4.0T                  |
| Track Count          | (~135–180 nm)       | (~100–125 nm)         | (~60–80 nm)                   |
+----------------------+---------------------+-----------------------+-------------------------------+
| Sacrificial Release  | None                | Mandatory dry vapor   | Dual-tier release &           |
| Etch Requirement     | (Bulk fin etch)     | SiGe selective etch   | Middle Dielectric Isolation   |
+----------------------+---------------------+-----------------------+-------------------------------+

Nanosheet Transistor Fabrication

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