nitride deposition

Silicon nitride (Si3N4) deposition by CVD produces thin films that serve critical roles throughout semiconductor device fabrication as gate dielectric liners, spacers, etch stop layers, passivation coatings, hard masks, stress engineering layers, and anti-reflective coatings. The two primary CVD methods for nitride deposition are LPCVD and PECVD, producing films with significantly different properties. LPCVD silicon nitride is deposited at 750-800°C using dichlorosilane (SiH2Cl2) and ammonia (NH3) in a low-pressure (0.1-1 Torr) hot-wall furnace. This produces near-stoichiometric Si3N4 films with high density (2.9-3.1 g/cm³), excellent chemical resistance to hot phosphoric acid and HF, high refractive index (2.0 at 633 nm), very low hydrogen content (<5 at%), high compressive stress (~1 GPa), and superior dielectric properties (breakdown >10 MV/cm). LPCVD nitride is the standard for applications requiring the highest film quality, including gate spacers and LOCOS/STI oxidation masks. PECVD silicon nitride is deposited at 200-400°C using SiH4 and NH3 (or N2) with RF plasma excitation. The lower temperature makes it compatible with BEOL processing but produces non-stoichiometric SiNx:H films with significant hydrogen content (15-25 at%), lower density, higher wet etch rate, and tunable stress. The Si/N ratio and hydrogen content can be adjusted by varying the SiH4/NH3 flow ratio, RF power, and frequency. PECVD nitride is extensively used as a passivation layer (protecting finished devices from moisture and mobile ions), copper diffusion barrier in BEOL stacks, and etch stop layer between dielectric layers. For stress engineering in advanced CMOS, PECVD nitride stress is tuned from highly compressive to highly tensile by adjusting deposition parameters — tensile nitride over NMOS and compressive nitride over PMOS transistors enhance carrier mobility through dual stress liner (DSL) techniques. ALD silicon nitride, deposited at 300-550°C, provides atomic-level thickness control and perfect conformality for sub-nanometer applications like spacer-on-spacer patterning at the most advanced nodes.