optimization hierarchical

**Hierarchical Optimization** in semiconductor manufacturing is a **multi-level optimization approach that optimizes at different structural levels** — from module-level recipe optimization, to integration-level process flow optimization, to fab-level throughput and cost optimization. **Optimization Levels** - **Unit Process**: Optimize individual recipes (etch rate, selectivity, uniformity) within each tool. - **Module**: Optimize across the lithography-etch module or the CVD-CMP module jointly. - **Integration**: Optimize the full process flow for electrical performance and yield. - **Factory**: Optimize tool utilization, cycle time, throughput, and cost. **Why It Matters** - **Decomposition**: Breaking a 1000-variable problem into hierarchical sub-problems makes it solvable. - **Consistency**: Each level's optimization must be consistent with the constraints from adjacent levels. - **Industry Practice**: Real fab optimization is inherently hierarchical — process engineers → integration engineers → fab management. **Hierarchical Optimization** is **optimizing at every scale** — from individual recipe parameters up through the entire factory, with each level informing the next.