overlay metrology

**Overlay Metrology** is the **measurement and control of the alignment accuracy between successive lithographic layers** — ensuring that features printed in one layer are correctly positioned relative to the previous layer, critical for device functionality. **What Is Overlay?** - Overlay error: Misalignment between current layer and previous layer. - Two components: Translation (dx, dy) and rotation (dR, dθ) and magnification. - Must be controlled to < 1/3 of the critical dimension (CD). - At 5nm node (CD=15nm): Overlay budget < 2nm total error. **Sources of Overlay Error** - **Wafer alignment error**: Inaccurate detection of alignment marks. - **Scanner lens distortion**: Non-ideal imaging field geometry. - **Thermal expansion**: Wafer and mask expand differently during exposure. - **Wafer deformation**: CMP, stress, thin films bow wafer → distortion of mark positions. - **Process-induced shift**: Film deposition or etch moves mark centers. **Overlay Measurement** - **Imaging Overlay (CD-SEM/OCD)**: Measure printed target pairs (box-in-box, bar-in-bar). - Large target (10–30μm): Accurate but far from device. - Small target: More representative but noisier measurement. - **Diffraction-Based Overlay (DBO/μDBO)**: Measure diffraction grating targets. - KLA ARCHER, ASML SMASH sensors. - Higher accuracy, smaller target size (< 5μm). - Measures overlay from asymmetric diffraction signal. **Overlay Control Loop** 1. Expose wafer with current layer recipe. 2. Measure overlay at dozens of sites across wafer. 3. Model overlay fingerprint (linear + higher-order terms). 4. Correct scanner lens corrections and stage offsets for next lot. 5. Optionally: Per-wafer APC (Advanced Process Control) correction. **EUV Overlay Challenges** - EUV mask magnification 4x → mask distortion contributes to overlay. - Stochastic variation in resist placement → pattern placement error. - Target: < 1.5nm overlay for 3nm node. Overlay metrology is **the cornerstone of multi-patterning and EUV yield** — every nanometer of overlay error consumed reduces the CD budget, and misaligned layers cause catastrophic device failures in SRAM and logic at sub-5nm nodes.