package height

**Package height** is the **overall vertical dimension of a semiconductor package from board-contact plane to top surface** - it determines z-axis clearance, stacking compatibility, and thermal-mechanical constraints. **What Is Package height?** - **Definition**: Specified maximum and nominal thickness in package outline drawings. - **Contributors**: Mold cap thickness, die stack, substrate, and terminal geometry all contribute. - **Application Impact**: Critical for slim devices, shield can clearance, and enclosure fit. - **Variation Sources**: Molding pressure, grind thickness, and warpage can alter measured height. **Why Package height Matters** - **Mechanical Fit**: Excess height can cause enclosure interference and assembly rejection. - **Product Design**: Height budget drives package selection in mobile and compact systems. - **Thermal Design**: Package thickness affects thermal path length to heat spreaders. - **Yield**: Height drift indicates upstream stack-up or molding process instability. - **Compliance**: Height specifications are often strict customer acceptance criteria. **How It Is Used in Practice** - **Stack-Up Control**: Manage die, substrate, and mold-cap thickness contributions with tight tolerances. - **Metrology SPC**: Track package-height distribution by lot and tool to detect drift early. - **Design Verification**: Revalidate enclosure and heat-sink clearance after package revisions. Package height is **a primary mechanical envelope parameter in package definition** - package height must be controlled as a cross-functional requirement spanning packaging, thermal, and product-mechanical design.