pecvd

**PECVD Silicon Nitride** is the **plasma-enhanced CVD deposition of hydrogen-rich SiN (SiNₓHᵧ) at moderate temperature (300-400°C) — enabling conformal coverage and tunable stress properties (tensile or compressive) — and serving as etch stop layers, spacers, and stress engineering material across CMOS manufacturing**. SiN is indispensable for advanced device integration. **Plasma-Enhanced CVD Process** PECVD SiN is deposited via RF plasma (13.56 MHz) using precursors SiH₄ or DIPS (diisopropylsilane) and NH₃ or N₂. The plasma activates decomposition at lower temperature (300-400°C vs 700-800°C for thermal CVD). Deposition rate is 10-100 nm/min depending on plasma power. The deposited nitride is hydrogen-rich (SiNₓHᵧ, with H ~5-15 wt%), which affects stress and etch rate. Conformal coverage is excellent even on high-AR features (>10:1) due to slow deposition rate and plasma activation. **Tensile vs Compressive Stress** SiN stress is tunable via RF frequency and power: (1) low RF frequency (60-100 kHz) with high power → tensile stress (50-200 MPa), (2) high RF frequency (13.56 MHz) with moderate power → compressive stress (-50 to -300 MPa). The mechanism involves: (1) ion bombardment (higher energy ions increase stress), (2) hydrogen content (more H → more compressive), (3) nitrogen content (more N → more tensile). Stress tuning is critical for strain engineering (eSMT): tensile SiN stress compresses the Si channel (for PMOS, enhancing hole mobility), while compressive SiN stress can be used selectively. **Stress Engineering for eMobility** Stressed silicon technology (sSMT) uses stressed films to modulate channel strain: (1) tensile SiN on NMOS → tensile strain in Si channel → electron mobility increase ~5-20%, (2) compressive SiN on PMOS → compressive strain → hole mobility increase ~5-30%. This is achieved by selective deposition or selective removal of stressed films over different device types. Modern FinFET processes integrate stress layers as part of the flow, achieving significant performance gain from strain engineering. **SiN as Etch Stop Layer** SiN is used as an etch stop layer in dual damascene and interconnect: between metal lines and overburden dielectric, or between sequential interconnect layers. SiN has high selectivity to oxide: HF etches SiO₂ at ~100 nm/min but SiN at <1 nm/min. This enables oxide etch with SiN etch stop. However, the etch must be carefully timed to avoid SiN damage (even slow etch damages SiN if over-etched). Typical SiN etch stop thickness is 15-30 nm. **SiN Spacer Deposition and Anisotropic Etch** SiN spacers around gate (after gate etch in gate-first process) isolate gate from S/D regions and control contact location. Spacer deposition is conformal (covers all surfaces); spacer etch is anisotropic (removes SiN from horizontal surfaces but not vertical sidewalls). Spacer etch uses RIE (SF₆ or NF₃ chemistry) with vertical ion incidence, leaving SiN on sidewalls only. Spacer thickness is critical: thin spacers (<20 nm) reduce junction-to-gate capacitance and improve electrostatics, but too-thin spacers allow source/drain dopant to encroach on gate. Spacer thickness is typically 30-50 nm for 28 nm node, 15-25 nm for 7 nm node. **SiN Optical Properties and ARC** SiN is used as an anti-reflection coating (ARC) in lithography: SiN (k=1.8-2.0, n~2.0) absorbs UV light and reduces reflectance from underlying layers, improving image contrast. SiN ARC thickness is tuned to minimize reflectance at the lithography wavelength (193 nm for ArF). SiN ARC is deposited conformally after gate etch (or other patterning step) and removes after lithography (before next etch). SiN thickness for ARC is ~50-100 nm. **SiN Passivation and Interface Quality** SiN is also used as a passivation layer (e.g., on completed device, before contacts). SiN provides: (1) mechanical protection, (2) moisture barrier (SiN is hydrophobic), (3) charge neutralization (SiN has fixed positive charge, helping deplete near-surface region in PMOS). SiN passivation quality depends on hydrogen content and deposition conditions. High-quality SiN (low defects, appropriate H content) provides excellent passivation. **NH₄F Wet Etch of SiN** SiN is selectively etched via wet chemistry: ammonium fluoride (NH₄F, ~20-40% aqueous solution) etches SiN at ~10-30 nm/min while leaving SiO₂ largely intact (SiO₂ etches at <1 nm/min). This selectivity enables SiN removal without attacking oxide. However, prolonged exposure to NH₄F attacks SiO₂ (slow etch), so etch time must be controlled. Buffered solutions (NH₄F + HF) can improve selectivity or adjust etch rate. **Hydrogen Content and Stress Relaxation** Hydrogen in PECVD SiN is critical to properties: (1) high H content → compressive stress, lower density, higher etch rate, better adhesion, (2) low H content → tensile stress, higher density, lower etch rate, poorer adhesion. However, hydrogen can evolve during thermal processing (above 200°C, hydrogen gas escapes), causing stress changes and cracking. Stress relaxation during subsequent anneals is a concern for reliability. **Comparison with LPCVD SiN** LPCVD SiN (deposited at 700-800°C using SiCl₂H₂ + NH₃) is stoichiometric Si₃N₄ with very low hydrogen. LPCVD SiN has higher density, lower etch rate, higher stress, and is commonly used for etch stop (due to superior chemical resistance). PECVD SiN is preferred for spacers and stress engineering (tunable stress). Dual-layer SiN (LPCVD + PECVD) is sometimes used: LPCVD outer layer (chemical resistance), PECVD inner layer (stress engineering). **Summary** PECVD silicon nitride is a versatile material in CMOS technology, providing conformal deposition, tunable stress, and strong etch selectivity. Its role in strain engineering, etch stops, and passivation makes it essential for advanced device performance.