photolithography
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Lithography is how a chip design becomes a physical pattern: light is projected through a patterned mask onto photoresist on the wafer, printing one circuit layer at a time. A leading-edge chip is built from dozens of these patterned layers stacked in tight registration, so the smallest feature a fab can print sets the practical limit for the node.
**Resolution comes down to wavelength and numerical aperture.** The Rayleigh relation is $\text{CD} = k_1 \cdot \lambda / \text{NA}$: critical dimension shrinks when the exposure wavelength gets shorter, the optics collect a wider cone of light, or the process pushes the empirical $k_1$ factor lower. The industry rode mercury i-line, then 248 nm KrF and 193 nm ArF deep-ultraviolet light for decades, stretched 193 nm with water immersion, and then moved the tightest layers to extreme ultraviolet at 13.5 nm.
**EUV is the marvel and the bottleneck.** At 13.5 nm, ordinary lenses do not work because EUV light is absorbed by almost everything, so the scanner operates in vacuum with reflective molybdenum-silicon multilayer mirrors. The light source fires a high-power laser at tin droplets tens of thousands of times per second to create plasma bright enough for production. ASML is the only company shipping these scanners at scale; current EUV tools are well over 150 million dollars, and High-NA systems are commonly discussed as several-hundred-million-dollar tools.
**Computation makes sub-wavelength printing manufacturable.** A mask is not a simple one-to-one drawing of the desired wafer pattern. Diffraction rounds corners, shortens line ends, and shifts edges, so computational lithography pre-distorts the mask with OPC, source-mask optimization, and inverse lithography. GPU-accelerated tools such as NVIDIA cuLitho matter because mask synthesis is now one of the most compute-heavy steps in the manufacturing flow.
**Below the resolution limit, patterning gets split.** Before EUV was production-ready, fabs printed the tightest layers by decomposing one design layer into multiple exposures or by using self-aligned spacers such as SADP and SAQP. EUV collapses many of those multi-mask sequences back into one exposure, reducing overlay risk and cycle time even though the scanner itself is extremely expensive.
| Generation | Wavelength | Where it is used |
|---|---:|---|
| i-line | 365 nm | Legacy, MEMS, coarse layers |
| KrF DUV | 248 nm | Mature nodes and non-critical layers |
| ArF DUV | 193 nm | Mature logic, memory, and many support layers |
| ArF immersion | 193 nm in water | 28 nm to 7 nm, often multipatterned |
| EUV | 13.5 nm | 7 nm to 2 nm critical layers |
| High-NA EUV | 13.5 nm | 2 nm and below as the ecosystem ramps |
```flowchart
{ "rows": [
{ "type": "nodes", "items": [
{ "title": "Coat resist", "sub": "spin-on film", "tone": "neutral" },
{ "title": "Soft bake", "sub": "remove solvent", "tone": "neutral" }
] },
{ "type": "arrow" },
{ "type": "group", "title": "Expose and develop", "note": "one mask layer at a time", "cycle": true, "loop": "repeats for every patterned layer", "items": [
{ "title": "Expose", "sub": "project mask", "tone": "green" },
{ "title": "Post bake", "sub": "drive chemistry", "tone": "green" },
{ "title": "Develop", "sub": "reveal pattern", "tone": "green" },
{ "title": "Inspect", "sub": "overlay and CD", "tone": "orange" }
] },
{ "type": "arrow" },
{ "type": "nodes", "items": [
{ "title": "Transfer", "sub": "etch or deposit", "tone": "orange" },
{ "title": "Strip resist", "sub": "prepare next layer", "tone": "neutral" }
] }
] }
```
**That is why lithography sits at the center of chip geopolitics and AI supply.** Access to the best scanners gates access to leading-edge patterning, export controls target exactly these tools, and every advanced AI accelerator depends on a small number of EUV systems running in a small number of fabs.