physical design hierarchical
**Hierarchical Physical Design** is the **divide-and-conquer methodology for implementing large SoCs where the chip is partitioned into independently designed blocks (macros/partitions) that are separately placed-and-routed, then assembled at the top level** — enabling parallel team execution, managing tool capacity for billion-transistor designs, and providing natural abstraction boundaries that keep implementation tractable, with modern SoCs typically having 10-50 hierarchical blocks assembled into a single chip.
**Why Hierarchy Is Necessary**
- Flat P&R of billion-gate SoC: Tool runtime = weeks, memory = terabytes → impractical.
- Hierarchical: Each block (50-200M gates) → manageable P&R in hours-days.
- Parallel execution: Multiple teams implement blocks simultaneously.
- IP reuse: Hard macro blocks (CPU, GPU, memory) used as-is.
**Hierarchical Design Flow**
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**Floorplanning Decisions**
| Decision | Impact | Constraint |
|----------|--------|------------|
| Block placement | Wirelength, timing, congestion | Data flow affinity |
| Block shapes | Aspect ratio, area utilization | Power grid alignment |
| Pin placement | Inter-block timing, routability | Feed-through, congestion |
| Power grid topology | IR drop, EM | Current per block |
| Channel width | Routing resources | Signal density |
**Interface Budgeting**
- Top-level creates timing budgets for each block boundary:
- Input arrival times at block input pins.
- Required arrival times at block output pins.
- Block must close timing within its budget.
- If block can't meet budget → renegotiate with top level → iterate.
**Abstract Views**
| View | Content | Used By |
|------|---------|--------|
| Physical abstract (LEF) | Block outline, pin locations, routing blockages | Top-level P&R |
| Timing abstract (Liberty) | Pin-to-pin timing arcs, constraints | Top-level STA |
| Power abstract | Current profile per mode | Top-level power analysis |
| Parasitic abstract | Simplified RC model | Top-level SI analysis |
**Challenges of Hierarchical Design**
- **Interface timing closure**: Block and top budgets must converge → requires iteration.
- **Feed-through routing**: Top-level signals may need to pass through block areas.
- **Power grid alignment**: Block and top-level power grids must connect seamlessly.
- **Placement legality**: Block boundaries must align to placement grid.
**Hybrid Approaches**
- **Hard macros**: Block layout frozen → used as black box at top level. No flexibility.
- **Soft macros**: Block placement is flexible → top-level tool can adjust in-context.
- **Mixed**: Some blocks are hard (reused IP), others soft (project-specific).
Hierarchical physical design is **the only viable methodology for implementing modern SoCs** — without hierarchical partitioning, the 10-50 billion transistors in flagship mobile and server processors would overwhelm any single EDA tool invocation, and the dozens of engineering teams working in parallel would have no structured way to integrate their work into a cohesive chip.