Planar Process
# The Planar Process: Oxide Masking, Lateral Patterning & Why the Junction Finally Went Under Glass
Every process this lineage has covered so far — point-contact whiskers, alloy regrowth, melt-dosed crystal pulling, double diffusion — controlled a junction's *depth* with increasing precision, but every one of them still left that junction's edge exposed to open air or a bare etched surface, the same surface-state problem the CP-4 chemical polish article identified back at the very first point-contact process step. Jean Hoerni's planar process, introduced at Fairchild in 1959, solved a problem none of those earlier processes had even tried to: it grew a protective layer of silicon dioxide directly on the wafer *before* diffusing anything, patterned that oxide with photolithography to open precisely placed windows, diffused dopant only through those windows, and then left the finished junction's edge sitting underneath undisturbed oxide rather than exposed at a cut mesa sidewall. The device surface stopped being something later steps had to protect against — it became something the process itself never exposed in the first place.
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## 1. Why Silicon Dioxide Works as a Diffusion Mask at All
Hoerni's process depends on one specific material property: common dopants like boron and phosphorus diffuse through thermally grown silicon dioxide thousands of times more slowly than they diffuse through silicon itself at the same furnace temperature. A layer of oxide only a fraction of a micrometer thick, grown everywhere a dopant should *not* enter, effectively blocks diffusion there while leaving diffusion free to proceed wherever a photolithographically etched window has removed that oxide down to bare silicon. The oxide itself grows according to the Deal-Grove model, in which oxidant must first diffuse through whatever oxide layer already exists before it can react at the silicon interface beneath it:
a relationship that is itself diffusion-limited at longer oxidation times — the same square-root-of-time character this entire process lineage keeps encountering, now governing how much oxide grows rather than how deep a dopant diffuses.
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## 2. Why the Junction's Edge Mattered More Than Its Depth
Every mesa-style device before the planar process — including diffused-junction transistors etched into individual mesas for isolation — necessarily exposed the p-n junction's edge where the mesa sidewall was etched, because that edge was, by construction, the boundary where the device's active region had been physically cut away from its neighbors. That exposed edge carries exactly the kind of high dangling-bond surface-state density the CP-4 chemical polish article identified in bare germanium: $D_{it} > 10^{13}\,\text{cm}^{-2}\text{eV}^{-1}$, a density large enough to generate substantial surface leakage current and long-term parametric drift, the same physics that made silicone wax potting necessary for the point-contact transistor decades earlier. Thermally grown silicon dioxide on silicon, by contrast, forms an exceptionally low-defect-density interface — roughly $D_{it}\sim10^{10}\,\text{cm}^{-2}\text{eV}^{-1}$, several orders of magnitude cleaner — and because the planar process's junction never exists without oxide already covering its lateral edge, that clean interface is what the junction terminates against instead of bare, etched silicon. The entire reliability gain the planar process is remembered for traces back to this single substitution: a native, high-defect-density exposed edge, replaced by a grown, low-defect-density oxide-capped one.
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## 3. Lateral Patterning: The Capability No Earlier Process Had At All
Every process in this lineage up through double diffusion controlled a junction's depth with increasing precision, but each one still treated an entire wafer face as a single, undifferentiated diffusion target — every point on the surface received the same dopant profile. The planar process's photolithographically patterned oxide windows broke that constraint for the first time: different regions of the same wafer face could now receive entirely different diffusions, isolated from each other by oxide that was never opened over them, enabling multiple independent transistors — and eventually, entire interconnected circuits — on a single piece of silicon. This lateral patterning capability, not simply the depth control this lineage had been refining since the point-contact transistor, is what turned "a better way to make one transistor" into "the foundation of the integrated circuit."
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## Planar Process's Place in the Process Lineage
| Process Decision | Diffused-Junction (mid-1950s) | Planar Process (1959) |
|---|---|---|
| Lateral patterning | None — whole-wafer diffusion | Oxide-masked windows, independently placed |
| Junction edge condition | Exposed at a cut mesa sidewall | Capped by undisturbed thermal oxide |
| Surface-state density at the edge | High ($D_{it}>10^{13}\,\text{cm}^{-2}\text{eV}^{-1}$) | Low ($D_{it}\sim10^{10}\,\text{cm}^{-2}\text{eV}^{-1}$) |
| Devices per wafer | Limited by mesa isolation geometry | Limited only by lithographic pattern density |
| Route to integration | None — isolated discrete devices | Direct — adjacent patterned regions become a circuit |
Read the planar process through a *never-expose-the-junction* lens rather than a *new masking trick* lens: the point-contact transistor needed silicone wax to protect a surface it could not avoid exposing; the planar process simply arranged for that surface never to be exposed in the first place, by making sure oxide, not air or an etched sidewall, was always the first thing grown over any junction edge the process ever created — and, as a direct side effect of solving that one problem, also handed the industry the lateral patterning capability every integrated circuit since has depended on.