plasma etch process
**Plasma Etch Processing** is the **dry etching technique that uses chemically reactive plasma to selectively remove material in patterns defined by lithography — providing the anisotropic (vertical) etch profiles essential for transferring nanometer-scale patterns from photoresist into device and interconnect layers, where control of etch rate, selectivity, uniformity, profile angle, and critical dimension defines the fidelity of pattern transfer at every step of semiconductor fabrication**.
**Etch Mechanism**
1. **Plasma Generation**: RF power (source: ICP or CCP at 13.56 MHz or higher) ionizes process gases (CF₄, Cl₂, HBr, SF₆, etc.) in a low-pressure chamber (1-100 mTorr), creating reactive species (radicals, ions, electrons).
2. **Chemical Etching**: Reactive radicals (F*, Cl*, Br*) diffuse to the wafer surface and react with the target material to form volatile products (e.g., SiF₄ from Si + F*). Chemical etching is isotropic (attacks in all directions).
3. **Physical Sputtering**: Ions accelerated by the DC bias bombard the surface vertically, providing directionality. Ion bombardment also enhances the chemical reaction rate at the surface being bombarded (ion-enhanced etching).
4. **Anisotropy**: The combination produces directional etching — vertical surfaces receive less ion bombardment (grazing angle) and are further protected by passivation layers (polymer deposition from carbon-containing gases like CHF₃ or C₄F₈). This achieves near-vertical sidewalls critical for sub-10 nm features.
**Key Etch Parameters**
| Parameter | Definition | Importance |
|-----------|-----------|------------|
| Etch Rate | nm/min of target removal | Throughput |
| Selectivity | Etch rate ratio (target/mask or target/stop layer) | Pattern fidelity, layer preservation |
| Anisotropy | (Vertical rate - Lateral rate) / Vertical rate | Feature profile control |
| Uniformity | Within-wafer etch rate variation (%) | CD uniformity across die |
| Microloading | Etch rate dependence on local pattern density | CD variation between dense/isolated features |
**Critical Etch Applications**
- **Gate Etch**: Defining the transistor gate with <1 nm CD control. Metal gate (TiN/TiAl/W) etch requires extreme selectivity to the underlying gate dielectric (HfO₂).
- **Fin/Nanosheet Etch**: High aspect ratio etch of the Si/SiGe superlattice stack to form nanosheets. Profile control through the multi-layer stack with different etch characteristics per layer.
- **Contact/Via Etch**: Etching high aspect ratio holes (>20:1) through dielectric to reach underlying metal or S/D contacts. Aspect Ratio Dependent Etching (ARDE) causes etch rate to slow in deeper features — compensation required.
- **3D NAND Channel Hole Etch**: The most extreme etch in semiconductor manufacturing — >100:1 aspect ratio holes through alternating oxide/nitride stacks (200+ layers). Requires specialized equipment with extreme ion energy control.
**Advanced Etch Techniques**
- **Atomic Layer Etching (ALE)**: Removes material one atomic layer at a time using self-limiting surface modification + gentle removal steps. ALE provides angstrom-level etch depth control, analogous to ALD for deposition. Essential for GAA channel release and critical dimension trimming.
- **Quasi-Atomic Layer Etching**: Pulsed plasma techniques that approximate ALE throughput with near-ALE precision.
- **Cryogenic Etching**: Substrate cooled to -100 to -120°C to enhance passivation layer formation and improve selectivity for deep silicon etching (MEMS, TSV).
Plasma Etch Processing is **the sculptor of semiconductor devices** — the subtractive patterning technology that carves nanometer-scale features into silicon, metal, and dielectric films with the precision and directionality required to define the transistors and interconnects of every modern integrated circuit.