power gating retention design

**Power Gating and Retention** is **the advanced low-power design technique that completely shuts off supply voltage to inactive circuit blocks using header or footer switch transistors, while selectively preserving critical register state in retention flip-flops to enable rapid wake-up without full reinitialization of the powered-down domain**. **Power Gating Switch Design:** - **Header Switch (PMOS)**: placed between global VDD and local virtual VDD (VVDD)—PMOS switches provide lower on-resistance per unit width and simpler gate drive but occupy more area than NMOS - **Footer Switch (NMOS)**: placed between local virtual VSS (VVSS) and global VSS—NMOS switches are smaller for equivalent resistance but require level-shifted gate drive and create ground bounce during switching - **Switch Sizing**: on-resistance must be low enough to limit IR drop across the switch network to <5% of VDD under peak current demand—typical switch density of 10-50 mΩ·μm² requires 5-15% of block area for switch cells - **Rush Current Control**: simultaneous turn-on of all switches creates massive inrush current as local capacitance charges—staged turn-on with daisy-chained enable signals limits peak current to 2-5x steady-state over 10-100 clock cycles **Retention Flip-Flop Architecture:** - **Balloon Latch**: a small always-on latch (connected to non-gated VDD) shadows the main flip-flop output—on sleep entry, SAVE signal transfers state to balloon; on wake-up, RESTORE signal returns state to main flip-flop - **Master-Slave Retention**: retention latch is integrated into the slave stage of the flip-flop, reducing area overhead to 15-25% compared to adding a separate balloon latch - **Save/Restore Timing**: SAVE must complete before power shutdown (typically 1-2 clock cycles); RESTORE must complete before functional clocks resume—incorrect sequencing causes state corruption **Power Gating Control Sequence:** - **Sleep Entry**: (1) complete pending transactions, (2) isolate outputs of power-gated domain, (3) assert SAVE to retention flip-flops, (4) disable clocks to power-gated domain, (5) assert sleep signal to switch cells in staged sequence - **Sleep Exit (Wake-up)**: (1) de-assert sleep signal with staged switch turn-on (10-100 cycles), (2) wait for VVDD to stabilize within 5% of VDD, (3) assert RESTORE to retention flip-flops, (4) enable clocks, (5) de-assert isolation, (6) resume operation - **Isolation Cells**: clamp outputs of power-gated domain to known values (0, 1, or last value) during shutdown—prevents floating outputs from causing short-circuit current in always-on logic - **Power Controller FSM**: always-on state machine manages the sleep/wake sequence, responding to hardware interrupts or software-controlled power management commands **Power Gating Implementation Challenges:** - **Power Network Design**: separate always-on VDD mesh and switchable VVDD mesh required—always-on network must maintain low IR drop for retention cells and isolation cells - **Verification**: UPF/CPF-driven power-aware simulation verifies correct behavior during all power state transitions, including unexpected scenarios like mid-transaction power-down and rapid sleep/wake cycling - **Wake-Up Latency**: total wake-up time ranges from 100 ns to 10 μs depending on switch network size and rush current limits—this latency determines the minimum idle period that makes power gating energy-efficient **Power gating with state retention is the most effective leakage reduction technique in modern SoC design, achieving 95-99% leakage power savings in shut-down domains while preserving the ability to resume operation within microseconds—making it essential for mobile, IoT, and datacenter chips that must balance peak performance with aggressive power management.**