power mosfet fabrication
**Power MOSFET** is the transistor optimized not for logic switching speed but for efficiently conducting large currents (1–1000 A) at high voltages (20–1200 V) with minimal conduction and switching losses — the workhorse of every voltage regulator, motor driver, DC-DC converter, and power delivery circuit in electronics. While logic MOSFETs in a CPU are measured in nanometers and picoamps of leakage, power MOSFETs are measured in milliohms of on-resistance ($R_{DS(on)}$) and amperes of drain current. Every AI server's power supply, every GPU voltage regulator module (VRM), and every battery charger depends on power MOSFETs to convert wall power into the precise voltages that chips consume.
**The key figure of merit — $R_{DS(on)} \times Q_g$.** A power MOSFET's quality is captured by two opposing metrics: lower on-resistance ($R_{DS(on)}$) means less conduction loss ($P = I^2 \cdot R_{DS(on)}$), but achieving low $R_{DS(on)}$ requires a large die with high gate capacitance ($Q_g$), which increases switching loss ($P_{sw} \propto Q_g \cdot V_{DS} \cdot f_{sw}$). The product $R_{DS(on)} \times Q_g$ (measured in mΩ·nC) is the technology figure of merit — lower is better, and it improves with each generation of trench-gate and charge-balance technology:
$$P_{\text{total}} = I_D^2 \cdot R_{DS(on)} + Q_g \cdot V_{DS} \cdot f_{sw} + \frac{1}{2} C_{oss} \cdot V_{DS}^2 \cdot f_{sw}$$
where the three terms are conduction loss, gate-charge switching loss, and output-capacitance loss respectively.
**Vertical vs lateral — why power MOSFETs are different.** Logic MOSFETs are lateral devices (current flows parallel to the wafer surface). Power MOSFETs are overwhelmingly **vertical**: current flows from the source on top, down through the channel, through the drift region (which sustains the blocking voltage), and out the drain on the wafer backside. This vertical topology lets the entire die area conduct current simultaneously — unlike lateral devices where only the channel edge carries current.
| Parameter | Logic MOSFET (5 nm) | Power MOSFET (trench) | Power MOSFET (SiC) |
|---|---|---|---|
| Voltage rating | 0.5–1.2 V | 20–200 V (Si) | 600–1700 V |
| Current rating | ~µA per fin | 1–300 A per die | 10–100 A |
| $R_{DS(on)}$ | N/A (digital) | 0.5–50 mΩ | 5–80 mΩ at 650V |
| Gate oxide | HfO₂ (high-k), 1–2 nm EOT | SiO₂, 30–70 nm | SiO₂, 40–50 nm |
| Channel length | 5–12 nm | 0.3–1 µm | 0.5–1.5 µm |
| Die size | ~100 mm² (GPU) | 2–30 mm² (power) | 4–36 mm² |
| Switching freq | 1–5 GHz (logic clock) | 100 kHz – 10 MHz | 50 kHz – 1 MHz |
| Key metric | Speed (fT) | $R_{DS(on)} \times Q_g$ | $R_{DS(on)} \times$ Area |
| Material | Si (strained) | Si | 4H-SiC (wide bandgap) |
**Trench-gate MOSFET — the dominant structure.** In a trench-gate power MOSFET, the gate electrode is buried in a trench etched into the silicon — the channel forms vertically along the trench sidewall. This eliminates the JFET resistance between adjacent cells (which plagues planar power MOSFETs) and allows extreme cell density (millions of parallel cells per mm²), minimizing $R_{DS(on)}$.
**Superjunction (SJ) — charge balance for high voltage.** For voltage ratings above ~100V, the drift region (which must be thick to block high voltage) dominates $R_{DS(on)}$. The superjunction structure interleaves alternating N and P columns in the drift region. In the off-state, mutual depletion between columns sustains the voltage across a much thinner drift region than a conventional device. The result: $R_{DS(on)}$ scales as $V_{BR}^{1.3}$ instead of the conventional $V_{BR}^{2.5}$ (Baliga limit), a ~10× improvement at 600 V.
**The silicon limit and wide-bandgap alternatives.** Silicon power MOSFETs face fundamental material limits: breakdown field (~0.3 MV/cm), thermal conductivity (1.5 W/cm·K), and carrier mobility constrain what a silicon device can achieve at high voltage. Wide-bandgap semiconductors push past these limits:
| Property | Si | 4H-SiC | GaN |
|---|---|---|---|
| Bandgap (eV) | 1.12 | 3.26 | 3.4 |
| Breakdown field (MV/cm) | 0.3 | 2.8 | 3.3 |
| Thermal conductivity (W/cm·K) | 1.5 | 4.9 | 1.3 |
| Electron mobility (cm²/V·s) | 1400 | 900 | 2000 (2DEG) |
| Saturated velocity (×10⁷ cm/s) | 1.0 | 2.0 | 2.5 |
| Baliga FOM (relative to Si) | 1× | ~600× | ~2000× |
SiC MOSFETs dominate 600–1700V applications (EV traction inverters, solar inverters, datacenter power supplies); GaN HEMTs dominate 20–650V at high frequency (laptop chargers, server VRMs, telecom power). Both are critical for AI datacenter power efficiency — a typical AI server rack consumes 40–80 kW, and every percentage point of conversion efficiency saved by GaN/SiC power stages reduces cooling cost and total energy consumption.
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**GaN power transistors for AI server VRMs.** The latest AI GPU power delivery uses 48V direct-to-chip architectures with GaN-based voltage regulators that convert 48V bus to ~0.75V core supply at 1–5 MHz switching frequency. GaN's zero reverse-recovery charge and low $Q_g$ enable these frequencies with >95% efficiency — impossible with silicon MOSFETs at the same voltage and current. Companies like EPC, GaN Systems (now Infineon), and Navitas supply the GaN FETs that power every H100/B200 training server's VRM.
**What power MOSFETs mean for the AI hardware stack.** A single 8-GPU AI training node consumes 5–10 kW. The power conversion chain (grid AC → 48V DC → 12V → 0.75V GPU core) passes through 6–10 power MOSFET stages per GPU. Each stage's efficiency compounds: 97% × 97% × 97% = 91% overall — meaning 500–900W is lost as heat in the power delivery alone. Moving from silicon to GaN/SiC at key stages recovers 2–5 percentage points, saving tens of thousands of dollars per rack per year in electricity at datacenter scale. Power MOSFETs are invisible to software engineers but are the physical bottleneck between the grid and the tensor cores.