Process Flow
A semiconductor process flow is the ordered route that turns starting material into a working device. It specifies which operations occur, what each operation receives and produces, and where measurements or decisions are required. A recipe controls how a particular operation runs; the flow connects those operations into a manufacturable structure.
The boundary must be stated. A wafer-fabrication flow may end at completed wafers or wafer test, while a broader product flow includes assembly, packaging, and final test. A short diagram of deposition, lithography, and etch is a useful explanation of one patterning module, not a complete route for every chip technology.
Follow the material, not just the machine names. In a simple subtractive patterning example, a film covers the substrate. Lithography forms openings in a resist layer. Etching removes exposed film while protected regions remain, then the resist is stripped. Each step changes the physical starting condition of the next one.
This example omits supporting operations such as cleaning, resist coating and baking, development, and measurement. Actual routes also use hard masks, selective processes, implantation, annealing, planarization, or other steps where needed. The point is the dependency: an etch requires the appropriate material stack and masking condition, not simply a reserved time on an etcher.
There is no universal ordering of deposition and patterning. A metal line can be formed by depositing a film and etching away unwanted material. In a damascene-style interconnect flow, trenches are first patterned into a dielectric, then lined and filled with metal; planarization removes the overburden. Similar-looking final features can require different intermediate structures and different controls.
Integration is the compatibility between steps. A film that passes its own thickness check may still fail the route if it cannot tolerate a later thermal treatment or cannot be removed selectively against the neighboring material. Surface cleanliness, topography, stress, thermal exposure, and chemical compatibility affect what can follow. An improved isolated step is not automatically an improved integrated process.
Changes therefore need downstream evaluation. Altering a clean can change the surface entering deposition. Changing a film can change its etch behavior. Adjusting planarization can change the surface presented to the next lithography layer. Process integration asks whether the entire sequence produces acceptable devices, rather than judging each operation only by its local output.
Measurements are decision points, not decorations. Metrology measures properties such as thickness, dimensions, or overlay. Inspection searches for defects. Electrical tests assess device behavior at appropriate stages. Their placement and sampling depend on the flow, the risk, and the available methods; not every wafer is measured after every operation.
An exception may trigger a hold, investigation, or an explicitly approved recovery path. Rework is not a universal undo operation. Some resist steps may allow an approved strip-and-repeat sequence, but an over-etch or an unintended implant cannot simply be reversed by rerunning the earlier step. Routes must distinguish recoverable conditions from irreversible changes.
Repeated tool visits do not mean repeated wafer states. A fab is re-entrant: wafers revisit deposition, lithography, etch, and other equipment families while different structures are being built. A later visit can use a different mask, recipe, material stack, and acceptance criterion. Treating every lithography visit as the same operation would lose the layer-specific meaning of the flow.
Front-end operations create device structures; contacts and interconnect operations connect them. Packaging and test extend the product route beyond wafer fabrication. These broad categories help navigation, but the actual sequence depends on the device architecture, integration scheme, and product requirements. Counting steps without defining what counts as one step is a poor way to compare technologies.
The executable route must preserve identity and revision. Manufacturing records need to establish which operation a wafer has completed, which route revision applies, and which qualified recipe or equipment path is permitted next. A lot split, experiment, hold, or approved alternate route should not erase that history. Scheduling selects among eligible resources; it does not authorize skipping a required operation.
Cycle time includes processing plus queues, transport, holds, and other delays within the chosen boundary. A shorter step list is not necessarily a faster or better flow: removing a useful clean or measurement can transfer risk downstream. Evaluate route changes against final device performance, yield, reliability, cycle time, and cost together.
The key idea: a process flow is a chain of physical dependencies backed by controls. Every operation must receive the right material state, create the required next state, and leave enough evidence for the wafer to proceed correctly.
Sources: ASML semiconductor manufacturing process overview; Lam Research deposition, etch, cleaning, and interconnect documentation. Illustrations are conceptual cross sections and measurement examples, not fabrication instructions.