pvt corner

**PVT Corner Analysis** is the **evaluation of design performance across all combinations of process variation (FF/SS/TT), supply voltage (±10%), and temperature (-40°C to 125°C) — ensuring timing closure, power, and leakage are acceptable across worst-case and typical conditions — essential for robust design and yield prediction**. PVT analysis is mandatory sign-off. **Process Corners (FF/SS/TT/FS/SF)** Process variation affects transistor speed and leakage: (1) FF (fast-fast) — devices are fastest (high transconductance, low threshold voltage), logic is fast, setup time tight, hold time loose, (2) SS (slow-slow) — devices are slowest (low gm, high Vt), logic is slow, setup time loose, hold time tight, (3) TT (typical-typical) — nominal device performance, (4) FS (fast process, slow interconnect) and SF (slow process, fast interconnect) — mixed. Extreme corners FF and SS bound timing paths. TT is nominal reference. **Voltage Variation (±10%)** Supply voltage variation affects timing: (1) high voltage (+10% above nominal, e.g., 1.1 V instead of 1.0 V) — devices faster (~3-5% timing improvement per 10% voltage increase, due to higher overdrive), (2) low voltage (-10%, 0.9 V) — devices slower (~3-5% degradation). Voltage variation originates from: (1) power delivery network (IR drop varies across die), (2) regulator tolerance (±5%), (3) system operation (frequency scaling, power gating). Worst-case timing assumes combination of worst-case process (SS) + worst-case voltage (low voltage). **Temperature Variation (-40°C to 125°C)** Temperature affects timing: (1) low temperature (-40°C) — higher mobility, devices faster, (2) high temperature (125°C) — lower mobility, devices slower (~5-10% degradation per 100 K). Temperature also affects leakage: (1) at low temperature, leakage minimal, (2) at high temperature, leakage increases exponentially (~doubles every ~50 K). Worst-case timing often at high temperature (slow) + low voltage (slow). Worst-case leakage at high temperature + high voltage. **Multi-Corner Multi-Mode (MCMM) STA** Static timing analysis (STA) is performed at multiple corners: (1) define corner (process, voltage, temperature combination), (2) load parasitic models (R, C, scaled to corner), (3) analyze all timing paths, (4) report timing (slack, violation). Tools (Primetime, Tempus) support MCMM: analysis at 100+ corners in single run, reporting worst-slack across all corners. Typical corners: FF/0.9V/40°C (hold), SS/1.1V/125°C (setup), TT/1.0V/85°C (nominal). Automated corner generation selects critical corners. **On-Chip Variation (OCV) Derating** On-chip variation (OCV) represents local process variation (cell-to-cell variation due to within-die variation, random mismatch). OCV is modeled as derating: path delay = nominal_delay × (1 + OCV_derating_factor). OCV derating varies per path: (1) paths on same power network have less variation, (2) spatially separated paths (opposite corners of die) have more variation. OCV can affect timing by ±10-15%. OCV is important for setup (pessimistic derating applied, conservative) and hold (derating opposite direction). **Advanced OCV (AOCV) and POCV** AOCV (advanced OCV) correlates variation to path slack: tight slack paths get large derating (pessimistic), loose slack paths get smaller derating (optimistic). This provides tighter margins on critical paths while maintaining slack margin. POCV (parametric OCV) correlates variation to physical location (die location) and cell properties (gate length, fin count). POCV is more accurate than OCV (handles spatial correlation) but requires more detailed models. **Hold and Setup Timing Across Corners** Setup timing (hold to next clock cycle) is worst at slow corners (slow data path, slow clock): SS/low-V/high-T. Hold timing (prevent spurious changes) is worst at fast corners: FF/high-V/low-T. Distinct corners optimize each: (1) setup analysis at SS corner, (2) hold analysis at FF corner. Modern STA tools (Primetime) simultaneously report both in single analysis (MCMM STA), ensuring all corners are checked. **Timing Margin and Yield Prediction** Timing margin is the slack remaining after applying all deratings and process variation. Positive margin = timing closure achieved. Negative margin = timing violations (design fails at worst corner). Typical yield target: 99%+ silicon (only <1% dies fail due to timing). Timing margin must be sufficient to cover: (1) random process variation (6-sigma limits), (2) systematic variation (topography, proximity), (3) aging (electromigration, PBTI/NBTI degradation over lifetime). Recommended margin: >50 mV (setup and hold combined) for robust yield. **Signoff Corner Selection** Design signoff uses 10-20 critical corners selected from hundreds possible: (1) extreme corners (FF/SS), (2) typical corner (TT), (3) power/temperature extremes (for leakage/thermal analysis). Foundry specifies required corners. Not all corners are equally critical: setup-critical corner might be SS/0.9V/125°C, but setup might not be most critical path class (might be hold-critical). Intelligent corner selection (based on design characteristics) reduces analysis effort while maintaining accuracy. **Summary** PVT corner analysis is comprehensive verification, ensuring timing closure across realistic process, voltage, and temperature ranges. Continued advances in AOCV and POCV models enable tighter margins and improved yield prediction.