qfn package

**QFN (Quad Flat No-Lead)** is a surface-mount IC package where all electrical leads are on the bottom perimeter — flush with or recessed into the package body — with no protruding gull-wing or J-leads. The die is mounted to an exposed copper die-attach pad (DAP) that doubles as the primary thermal path to the PCB. Key construction elements: silicon die wire-bonded to a copper lead frame, encapsulated in epoxy mold compound, with the bottom DAP and perimeter leads solderable directly to PCB land patterns. **Thermal performance** is the QFN's main advantage over leaded packages: the exposed DAP conducts ~50–80% of heat, achieving junction-to-board resistance of 7–12 C/W versus 35+ C/W through wire-bond leads alone. PCB thermal vias under the DAP further reduce impedance. **Signal integrity**: bond wires (25 µm Au or 20 µm Cu) add inductance (~1 nH/mm) and limit RF bandwidth — typically usable to ~6 GHz. For >10 GHz or high-power applications, flip-chip or HVQFN variants with integrated ground planes are preferred. **Manufacturing**: QFN packages are produced on copper lead frames, molded in strip format, and singulated by saw dicing. They are assembled via SMT reflow at 260°C peak (SAC305 solder), with stencil printing controlling thermal pad voiding to <25% for reliable Rth. **AI/ML context**: QFN is standard for edge AI support ICs — PMICs, clock buffers, SerDes retimers, and small inference accelerators (<5W). Large AI training/inference chips (>50W) require flip-chip BGA due to thermal and I/O density requirements that QFN cannot meet. ```svg ```