retrograde well
**Retrograde Well** is a **well implant profile where the peak dopant concentration is located below the surface** — improving latch-up immunity and reducing well resistance without degrading surface channel mobility in advanced CMOS transistors.
**Standard vs. Retrograde Well**
- **Standard Gaussian Profile**: Peak concentration at surface, decreasing with depth.
- Problem: High surface doping raises Vt, degrades inversion layer mobility.
- **Retrograde Profile**: Low surface concentration, peak at depth (0.3–0.7 μm).
- Achieved by: High-energy implant (MeV range for deep peak) + low-dose surface.
- Or: High-energy retrograde + surface counter-doping.
**Latch-up Improvement**
- Latch-up: Parasitic PNPN thyristor in CMOS triggers at high current → latches on.
- Key parameter: $\beta_{NPN} \times \beta_{PNP} < 1$ required to prevent latch-up.
- Deep retrograde peak: Reduces well resistance $R_{well}$ and substrate resistance $R_{sub}$.
- Lower $R_{well}$: Parasitic BJT base floated less — $\beta$ product reduced → better latch-up.
**Threshold Voltage Control**
- Low surface well doping → low body effect coefficient ($\gamma$).
- Better Vt control vs. retrograde body doping.
- Multiple implants create desired channel profile: Super-steep retrograde (SSR) for sub-100nm.
**Process Implementation**
- Standard: Phosphorus or arsenic (N-well), boron or BF2 (P-well).
- Energies: 200 keV–2 MeV for retrograde profiles (requires high-energy implanter or MeV implant).
- EPI (epitaxial layer) approach: Lightly-doped epi on heavily-doped substrate creates natural retrograde.
**EPI + Retrograde Well**
- SOI-like punch-through stopper: Extra boron implant below channel blocks subthreshold punch-through without raising surface Vt.
- Used in FinFET: Well doping in fin bulk region below gate.
Retrograde well engineering is **a standard technique at sub-90nm nodes** — balancing latch-up immunity, threshold voltage, and body effect in the three-dimensional doping landscape of modern CMOS.