self aligned contact

**Self-Aligned Contact (SAC)** is a **contact formation technique where the contact etch is guided by surrounding dielectrics rather than by lithographic alignment** — allowing contacts to be landed precisely on source/drain and gate without requiring precise overlay, enabling contact pitch scaling beyond lithography limits. **The Contact Alignment Problem** - As transistors scale, contacts must land on very small S/D regions (< 20nm wide). - Lithographic overlay error ± 5nm makes contact landing risky — misaligned contacts short to gate. - Solution: Let chemistry control contact landing, not alignment. **SAC Mechanism** - Gate electrode: Capped with SiN or SiCN dielectric cap (hard cap). - Spacers: SiN — etch resistant. - Contact etch chemistry: High selectivity to SiN cap and spacers, etches SiO2 fast. - Result: Even if contact hole overlaps the gate, etch stops on SiN cap — no shorting. - Contact self-aligns between spacers on S/D silicide region. **Process Requirements for SAC** - Gate SiN cap thickness: 30–60nm — must survive contact etch. - Gate SiN cap deposition: Blanket SiN after gate CMP, patterned to cover gate tops. - SAC etch chemistry: C4F6/C4F8/O2 plasma — high SiO2:SiN selectivity (10:1 to 20:1). - Self-alignment tolerance: Contact can overlap gate by up to gate cap thickness / etch selectivity without shorting. **Gate Contact (Gate SAC)** - Borderless gate contact: Landing on gate top, self-aligned to gate nitride cap sides. - Critical for SRAM access transistor — gate contact close to S/D contact. **SAC at Sub-5nm Nodes** - FinFET: SAC contacts between adjacent fins and gate — AR > 10:1. - GAAFET: SAC even more critical — gate-to-contact spacing ~ 4nm. - Selective deposition of contact metal (CVD Co, W) instead of PVD for conformal SAC fill. Self-aligned contacts are **the essential enabler of contact scaling below 20nm pitch** — without SAC, the tight gate-to-contact spacing of advanced FinFET and GAAFET nodes would cause catastrophic yield-killing shorts.