semiconductor ald atomic layer deposition

**Atomic Layer Deposition (ALD)** is the **ultra-precise thin-film deposition technique that grows material one atomic layer at a time through alternating, self-limiting chemical reactions — achieving sub-angstrom thickness control, perfect conformality on extreme topographies, and atomic-level composition uniformity that makes it indispensable for depositing gate dielectrics (HfO₂), metal gates (TiN), spacers (SiN), and barrier layers where even one monolayer of thickness variation is unacceptable at the 3nm node and below**. **Self-Limiting Growth Mechanism** ALD exploits the fact that certain chemical reactions saturate — once all available surface sites have reacted, additional precursor molecules find no binding sites and are purged away. One ALD cycle: 1. **Pulse Precursor A**: Trimethylaluminum (TMA) molecules adsorb to surface hydroxyl (-OH) groups, reacting with one -OH per TMA. Excess TMA does not react (self-limiting). Byproduct: CH₄. 2. **Purge**: Inert gas (N₂ or Ar) removes unreacted TMA and byproducts. 3. **Pulse Precursor B**: Water (H₂O) reacts with the adsorbed -Al(CH₃)₂ groups, replacing methyl groups with -OH and forming one monolayer of Al₂O₃. Self-limiting. 4. **Purge**: Remove excess H₂O and byproducts. Result: Exactly one monolayer (~1.0-1.2 Å) of Al₂O₃ per cycle, regardless of dose time (as long as saturation is achieved). **Key Advantages** - **Thickness Control**: Digital control — thickness = (number of cycles) × (growth per cycle). 100 cycles = 10nm ± 0.1nm. No other deposition technique achieves this precision. - **Conformality**: Because the reaction is surface-limited, every exposed surface receives the same monolayer regardless of geometry. ALD can coat the inside of 50:1 aspect ratio trenches uniformly. CVD and PVD cannot. - **Uniformity**: Wafer-to-wafer thickness uniformity <0.5%. Within-wafer uniformity <1%. The self-limiting nature eliminates sensitivity to precursor flux non-uniformity. **Critical Applications** - **High-k Gate Dielectric**: HfO₂ (k~20) deposited by ALD replaces SiO₂ (k=3.9) as the gate dielectric from 45nm onward. Thickness: 1.5-3nm. Requires atomic-level control because every monolayer affects threshold voltage. - **Metal Gates**: TiN, TaN, and TiAl deposited by ALD with precise work-function tuning through composition control. The difference between NMOS and PMOS threshold voltage is set by <1nm of compositional variation. - **Spacers**: SiN or SiCN spacers on gate sidewalls require perfect conformality to protect the gate during source/drain implant. **Limitations** - **Throughput**: 1-2 Å/cycle at 1 cycle per 2-10 seconds. A 10nm film requires 100 cycles = 200-1000 seconds. Much slower than PECVD (100nm/min). Spatial ALD (rotate wafer through precursor zones) and batch ALD (process 100+ wafers simultaneously) partially address throughput. - **Temperature Range**: Thermal ALD requires 200-400°C. Plasma-Enhanced ALD (PEALD) enables lower temperatures (50-200°C) for back-end-of-line and temperature-sensitive substrates. Atomic Layer Deposition is **the atomic-precision construction tool of the semiconductor fab** — building films one atomic layer at a time with a perfection that no other deposition technique can match, enabling the gate stacks and barriers that make sub-5nm transistors possible.