semiconductor defect inspection

**Semiconductor Defect Inspection** is the **systematic detection and classification of physical defects on the wafer surface during fabrication — identifying killer particles, pattern defects, film delaminations, and contamination events at each critical process step so that excursions are caught in hours rather than weeks, preventing the shipment of defective dies and enabling rapid root-cause analysis**. **Why Inspection Is Yield-Critical** A single 50 nm particle on a critical layer can kill a die worth hundreds of dollars. In a fab running 100,000 wafers per month, a yield-limiting defect mechanism that goes undetected for 24 hours can destroy millions of dollars in product. Inline inspection after every critical process step creates a safety net that catches excursions immediately. **Inspection Technologies** - **Broadband Brightfield Inspection**: Illuminates the wafer with broadband light and images the reflected pattern. Defects appear as anomalies in the expected pattern. Tools like KLA 39xx series achieve pixel sizes ~30 nm and capture pattern defects (bridging, opens, CD violations) as well as particles. High sensitivity but moderate throughput. - **Darkfield Laser Scanning**: A focused laser scans the wafer; only scattered light (from defects or particles) is collected. The patterned surface produces minimal scatter, so defects stand out with high signal-to-noise ratio. Extremely high throughput (>100 wafers/hour at relaxed sensitivity) — used as the primary defect monitoring tool for particles and large pattern defects. - **E-beam Inspection**: A scanning electron beam images the wafer at resolution comparable to CD-SEM. Captures defects invisible to optical inspection (sub-20 nm particles, buried voids, electrical defects through voltage contrast). Throughput is very low (~1 wafer/hour for small areas) — used for targeted review of critical areas, not full-wafer scanning. - **E-beam Review (Defect Review SEM)**: After optical inspection identifies defect coordinates, a high-resolution SEM revisits each defect site for classification. Automated Defect Classification (ADC) algorithms categorize defects by type (particle, scratch, residue, pattern) and feed the data into yield management systems. **Kill Ratio Analysis** Not all detected defects kill dies. The kill ratio (fraction of detected defects that cause electrical failure) varies by defect type and location. Yield engineers correlate inline defect maps with end-of-line electrical test data to determine which defect types and sizes are yield-relevant — focusing inspection resources on the defect modes that actually matter. **Defect Pareto and Excursion Control** Inspection data is aggregated into defect Pareto charts showing the top defect types by frequency and kill ratio. Statistical process control (SPC) charts track defect density per layer over time. Excursions (sudden spikes above the control limit) trigger immediate hold actions — wafers are quarantined until the root cause is identified and corrected. Semiconductor Defect Inspection is **the immune system of the fab** — continuously scanning every wafer for anomalies that threaten yield, and raising the alarm fast enough for engineers to cure the disease before it spreads through the production line.