semiconductor failure analysis
**Semiconductor Failure Analysis (FA)** is the **systematic investigation of failed integrated circuits to identify the root cause of electrical failure** — using a combination of electrical fault isolation, non-destructive imaging, and destructive physical analysis techniques including focused ion beam (FIB), emission microscopy (EMMI), and transmission electron microscopy (TEM) to locate defects at the nanometer scale, essential for yield improvement, reliability qualification, and customer return analysis.
**FA Workflow**
```
[Failed device from test / customer return / reliability test]
↓
Step 1: Electrical Verification
- Reproduce failure on ATE
- Classify failure mode (stuck-at, leakage, timing, parametric)
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Step 2: Non-Destructive Fault Isolation
- EMMI (photon emission microscopy)
- OBIRCH/TIVA (thermal-stimulated imaging)
- Lock-in thermography
→ Narrow defect location to ~µm area
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Step 3: Circuit Analysis / Targeted Deprocessing
- Backside polishing or decapsulation
- FIB cross-section at suspected location
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Step 4: Physical Analysis
- SEM imaging of defect
- TEM for atomic-level analysis
- EDS/EELS for chemical composition
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Step 5: Root Cause Determination
- Correlate defect with failure mode
- Report: process deviation, design weakness, or contamination
```
**Key FA Techniques**
| Technique | Full Name | What It Detects | Resolution |
|-----------|-----------|----------------|------------|
| EMMI | Emission Microscopy | Hot carrier emission, oxide breakdown, latch-up | ~1 µm |
| OBIRCH | Optical Beam Induced Resistance Change | Resistive shorts/opens, voids | ~0.5 µm |
| TIVA | Thermally Induced Voltage Alteration | Defective transistors, junctions | ~0.5 µm |
| EOFM | Electro-Optical Frequency Mapping | Logic state mapping | Gate level |
| FIB | Focused Ion Beam | Cross-section, circuit edit | ~10 nm |
| TEM | Transmission Electron Microscopy | Atomic structure, interfaces | ~0.1 nm |
| EDS/EDX | Energy Dispersive X-ray Spectroscopy | Elemental composition | ~1 nm |
**FIB (Focused Ion Beam)**
- Uses focused Ga⁺ or Xe⁺ ion beam to mill, image, and deposit material.
- Cross-sectioning: Cut precise trenches to expose buried structures for SEM/TEM viewing.
- Circuit edit: Cut metal lines (open circuit) or deposit metal (short circuit) → modify chip for debug.
- Nano-probing: Expose buried contacts for electrical measurement.
- Resolution: ~5-10 nm milling precision.
**EMMI (Emission Microscopy)**
- Failed transistors emit photons (hot carrier emission, oxide breakdown light).
- InGaAs camera: Detects near-infrared photons through silicon backside.
- Backside analysis: Polish silicon substrate to ~50 µm → image through backside.
- Can detect: Gate oxide breakdown, junction leakage, ESD damage, latch-up.
**Common Failure Modes Found by FA**
| Failure Mode | Physical Defect | FA Detection |
|-------------|----------------|---------------|
| Line open | Void in metal, electromigration | FIB cross-section, OBIRCH |
| Line short | Metal bridging, contamination particle | SEM, EDS |
| Gate oxide breakdown | TDDB, ESD damage | EMMI, TEM |
| Contact resistance | Poor silicide, underetch | TEM, resistance mapping |
| Parametric shift | Process variation, strain variation | Statistical analysis |
**Advanced FA for Sub-5nm**
- Backside analysis is mandatory: >10 metal layers block front-side access.
- Atom probe tomography (APT): 3D atomic-scale chemical mapping.
- FIB-TEM: FIB prepares <50 nm lamella → TEM images at atomic resolution.
- Challenge: Nanometer-scale defects in 3D structures (GAA, 3D NAND) are extremely difficult to locate.
Semiconductor failure analysis is **the detective work that connects electrical failures to physical defects** — without FA, manufacturing yield improvement would be impossible because engineers would never know what physical mechanism caused a chip to fail, making FA the essential feedback loop between fabrication, design, and test that enables the semiconductor industry to achieve the astounding defect densities required for manufacturing billions of functional transistors per chip.