semiconductor test wafer

**Semiconductor Testing** is the **quality assurance and yield verification discipline that validates every manufactured die against functional, parametric, and reliability specifications — using Automatic Test Equipment (ATE) at wafer probe (pre-packaging) and final test (post-packaging) to screen defective parts, characterize process performance, and ensure that only conforming devices reach customers at defect rates measured in parts per billion**. **Test Flow** 1. **Wafer Sort (Probe Test)**: After wafer fabrication, each die is contacted by a probe card (needles touching bond pads) and tested by ATE. Tests include continuity, leakage, basic functionality, and parametric measurements. Defective dies are inked or mapped for rejection. Identifies ~80-90% of defective dies before the expensive packaging step. 2. **Packaging**: Good dies are diced, wire-bonded or flip-chipped, and encapsulated. 3. **Final Test**: Packaged devices are tested on ATE through the package pins/balls. Full functional testing at speed (GHz clock rates), parametric characterization (Iddq, I/O levels, timing margins), and stress screening (burn-in at elevated voltage and temperature to accelerate infant mortality failures). 4. **System-Level Test (SLT)**: For complex SoCs, the packaged device boots an OS and runs real software. Catches defects that structural and parametric tests miss — protocol compliance, firmware interaction, multi-die coherency. **ATE Architecture** - **Pin Electronics**: Per-pin driver (sends signals at GHz rates) and comparator (measures device response within voltage and timing windows). Modern ATE supports 256-2048 pins simultaneously. - **Pattern Generator**: Stores and delivers billions of test vectors (input patterns + expected responses). For a modern SoC, the test pattern set may exceed 100 GB. - **DSP/RF Instruments**: On-ATE instruments test analog functions (ADC/DAC linearity, PLL jitter, RF gain/noise figure) without external equipment. - **Parallel Test**: Testing multiple devices simultaneously (multi-site, typically 4-32 sites) amortizes ATE cost. Site-to-site correlation is critical — all sites must produce identical test results. **Test Metrics** - **Test Coverage**: Percentage of potential defects detected by the test program. Stuck-at fault coverage >99%, transition fault coverage >95% are typical targets. - **DPPM (Defective Parts Per Million)**: Target for automotive: <1 DPPM (approaching parts per billion). Consumer: <100 DPPM. - **Test Time**: Directly determines test cost (ATE costs $50-200/hour). A smartphone SoC may require 2-5 seconds of test time. Reducing test time by 10% saves millions annually in high-volume production. - **Yield Loss (Overkill vs. Underkill)**: Overkill = rejecting good dies (lost revenue). Underkill = shipping bad dies (customer returns, reputation damage). The test limits must balance both. **DFT (Design for Testability)** Modern chips include dedicated test circuitry: scan chains (observe/control internal flip-flops), BIST (Built-In Self-Test for memories and logic), and JTAG (boundary scan for board-level connectivity). DFT structures typically consume 5-15% of die area but enable the high test coverage that makes sub-DPPM quality achievable. Semiconductor Testing is **the final quality gate between fabrication and the customer** — the discipline that converts wafers of uncertain quality into guaranteed-specification products through systematic electrical verification at speeds and volumes that match the manufacturing throughput of the world's most advanced fabs.