sequential 3d integration

```svg ``` **Sequential 3D Integration (S3D)** is a **monolithic 3D integration approach that fabricates multiple device layers sequentially on the same wafer** — building a second transistor layer directly on top of the first, connected by high-density inter-tier vias, without wafer bonding. **S3D Process** - **Bottom Tier**: Fabricate bottom transistors using standard high-temperature processes. - **Interlayer**: Deposit and planarize an interlayer dielectric on top of the bottom tier. - **Top Tier Channel**: Form the top-tier channel by epitaxy, wafer transfer, or laser crystallization. - **Top Tier Devices**: Fabricate top transistors using reduced-temperature processes (≤650°C to protect bottom tier). **Why It Matters** - **Density**: Doubles the transistor density per area without shrinking device dimensions. - **Inter-Tier Vias**: Monolithic vias can be ~100 nm diameter (vs. ~1 μm for bonded 3D) — enabling fine-grained connectivity. - **CFET Enabler**: Sequential 3D is the pathway to CFET (complementary FET with NMOS on top of PMOS). **Sequential 3D** is **stacking transistors one floor at a time** — building multiple active device layers monolithically for unprecedented transistor density.