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**SiC Dry Etching** is the **plasma-based etching of silicon carbide (SiC) using aggressive chemistry (SF₆/O₂ or Cl₂-based plasma) and high bias power — overcoming the high bond strength (4.5 eV Si-C vs 2.3 eV Si-O) to enable trench and feature patterning in power devices and RF applications**. SiC etch is more demanding than Si/SiO₂ etch. **High Bond Strength and Etch Challenge** SiC has extremely high bond strength (Si-C bond energy ~4.5 eV, Si-O ~2.3 eV, Si-Si ~2.2 eV), making it resistant to chemical attack and ion bombardment. Conventional Si etch chemistry (CF₄) is ineffective for SiC due to low reactivity. High-power plasma and aggressive chemistry (F or Cl radicals, or SF₆) are required. Etch rate is typically slow (~50-200 nm/min vs 500+ nm/min for Si), demanding high bias power and long etch times. **SF₆/O₂ Chemistry** SF₆/O₂ plasma is the primary etch chemistry for SiC. SF₆ (sulfur hexafluoride) dissociates in plasma to F radicals and F⁺ ions. F attacks C and Si in SiC, forming volatile products (SiF₄, CF₄, CF₂). O₂ oxidizes carbon, facilitating C removal. The SF₆:O₂ ratio is tuned to balance F availability (higher SF₆ favors C removal) vs O availability (higher O₂ favors etch rate). Typical ratio is 1:1 to 2:1 (SF₆:O₂). Temperature is moderate (room temperature to 100°C) and ICP power is high (500-2000 W). **Cl₂-Based Chemistry** Chlorine-based plasma (Cl₂ alone, or Cl₂ + HCl or Cl₂ + BCl₃) is an alternative to SF₆/O₂. Cl₂ is less aggressive than SF₆ but produces cleaner sidewalls and lower surface roughness. Cl₂ etch produces SiCl₄ (volatile) and CCl₄ (volatile). Cl₂ chemistry is preferred when surface roughness must be minimized (e.g., cavity resonator etching). However, Cl₂ etch rate is lower than SF₆/O₂ (~50 nm/min vs 150 nm/min typical). **High Bias Power and Anisotropy** SiC etch requires high RF bias power (200-500 W) to provide energetic ion bombardment necessary to break Si-C bonds. High bias power accelerates Ar⁺ or other ions toward the substrate, delivering energy for sputter-assisted chemical etch. The high bias power creates anisotropic etch profile (vertical, not undercut). Trench sidewalls are more vertical at higher bias power, but increased bias also increases damage. **Trench Etching for Power Devices** In SiC power devices (JBS diode, trench MOSFET), deep trenches (~1-5 µm depth, 0.5-2 µm width, AR 2:1 to 5:1) are etched to form device structures. SiC etch proceeds in multiple steps: (1) initial fast etch (high bias, large recess), (2) slower controlled etch (lower bias, AR fill, avoid voids), (3) surface cleanup etch if needed. Trench etching is challenging due to: (1) aspect ratio increase as etch proceeds (higher AR → slower etch due to ion depletion), (2) sidewall damage accumulation, and (3) tendency for narrowing (sidewall passivation). **Sidewall Roughness Control** SiC etch naturally produces rough sidewalls (LWR ~10-20 nm, LER ~5-15 nm) due to: (1) ion bombardment damage (creates rough surface), (2) preferential etch at defects, (3) photoresist mask roughness. Roughness is critical for power devices: rough sidewalls increase scattering and reduce device performance. Roughness is reduced by: (1) smooth photoresist mask (high-resolution lithography), (2) optimized plasma chemistry (Cl₂ produces smoother than SF₆), (3) lower bias power (reduces sputtering damage), (4) lower temperature (slower etch, smoother). Post-etch oxidation (thermal oxidation or plasma) can smooth sidewalls by oxidizing roughness peaks. **Etch Mask Selectivity** Standard SiO₂ photoresist masks have low selectivity to SiC (photoresist:SiC etch ratio ~1:3 to 1:5, meaning photoresist is attacked 20-50% as fast as SiC). This limits etch depth on photoresist alone (overetch removes mask). Hard masks (SiO₂, SiN, Ni) improve selectivity: SiO₂:SiC ~1:50 (SiC 50x faster), SiN:SiC ~1:100, Ni:SiC ~1:1000. Nickel hardmask is excellent for selectivity but is difficult to remove (strong Ni attachment to SiC). SiO₂ hardmask is standard, requiring thin mask (~200-500 nm) and careful control to avoid mask erosion. **Post-Etch Damage and Removal** Ion bombardment during etch creates surface damage layer (amorphous Si-C, lattice defects) ~20-50 nm thick. This damage increases leakage and reduces device breakdown voltage. Damage is removed via: (1) etching (further wet oxidation then HF etch), (2) post-etch annealing (high temperature in inert gas to recrystallize surface), or (3) oxidation (thermal oxidation transforms damaged layer to SiO₂, which is then removed). Post-etch annealing at 1000°C+ for 30 min can remove damage but is expensive and may degrade nearby structures. **Etch Rate and AR Effects** As trench etches deeper, ion density decreases (ions must travel farther to bottom), and etch rate slows. This "aspect ratio effect" (AR effect) causes non-uniform etch: shallow regions etch faster, deep regions slower. For uniform etching, the recipe must be optimized for the expected final AR, or multiple etch steps with different recipes are used. AR >5:1 becomes problematic: etch rate reduction >50% limits trench depth achievable with photoresist mask. **Summary** SiC dry etching is a challenging but essential process for power devices and RF circuits. High bond strength and high-AR features demand aggressive plasma chemistry and careful process control to achieve acceptable etch rate, selectivity, and surface quality.