Silicon Grown Junction 1954 Position Base Wire

# Position Base Wire: Gold-Gallium Alloy Selection, Binary Yield, and Touchdown Compliance

With the microscopic coordinates of the invisible $25\ \mu\text{m}$ base stripe mapped and locked into the micromanipulator in Step 29, technicians must now position the physical base contact wire directly over the crystal. In silicon technology, wire metallurgy is dictated by rigid thermodynamic and doping constraints: while germanium transistors used gold-indium or gold-antimony wires, silicon requires an acceptor element that dissolves readily in liquid gold-silicon eutectic and regrows as a degenerate $p^{++}$ ohmic contact. Texas Instruments selected fine gold-gallium ($99.5\%\ \text{Au}, 0.5\%\ \text{Ga}$) and aluminum alloy wires ($25\text{ to }50\ \mu\text{m}$ diameter) formed into chisel points. Unlike earlier continuous process trade-offs—such as balancing chemical etch depth or furnace pull speeds—base wire placement is an unforgiving binary outcome: the wire tip either lands squarely within the $25\ \mu\text{m}$ base stripe, yielding a functional transistor, or it strays by as little as $6\ \mu\text{m}$, bridging the adjacent collector or emitter junctions and producing catastrophic short circuits.

## 1. Wire Metallurgy: Gold-Gallium Eutectic Alloying and Acceptor Doping

Selecting the base wire alloy requires balancing low-temperature eutectic wetting against high solid-solubility acceptor doping:
1. The Role of the Gold Carrier:
Pure gold forms a deep eutectic with silicon at $363^\circ\text{C}$ ($18.6\ \text{at}\%\ \text{Si}$). This relatively low eutectic temperature allows localized bonding without heating the remainder of the bar. However, pure gold alloyed to $p$-type silicon yields inconsistent contact resistance.
2. Gallium as the Shallow Acceptor Dopant:
Texas Instruments incorporated $0.5\%\text{ to }1.0\%$ gallium into high-purity gold wire:
* Shallow Activation Energy: In silicon, gallium has an ionization energy of $E_a = 0.065\ \text{eV}$, remaining fully ionized even at low temperatures, unlike indium ($E_a = 0.16\ \text{eV}$) which freezes out carriers.
* Degenerate $p^{++}$ Regrowth: During electrical discharge bonding (Step 31), gallium dissolves into the liquid Au-Si eutectic pool. Upon rapid quenching, gallium rejects into the regrowing single-crystal silicon at solid-solubility levels ($N_A > 10^{19}\ \text{cm}^{-3}$). This heavily doped interlayer ensures quantum mechanical hole tunneling, keeping base resistance $R_B < 50\ \Omega$.
3. Chisel-Point Geometry:
Standard $0.002\text{-inch}$ ($50\ \mu\text{m}$) wire is too wide to land inside a $25\ \mu\text{m}$ base stripe without bridging. Technicians electrochemically etch the wire tip in potassium cyanide or aqua regia, tapering the contact footprint to a chisel point $10\text{ to }15\ \mu\text{m}$ across.

## 2. Real Diagram: Binary Placement Geometry and Touchdown Compliance

## 3. The Mathematics of Binary Placement Yield and Overlap Catastrophe

Base wire positioning is governed by strict probability mechanics and zero-tolerance physical constraints:
1. Stacked Placement Error Budget:
The error distribution of the positioned wire tip combines three independent Gaussian variations:
* Electrical Location Uncertainty (Step 29): $\sigma_{\text{loc}} \approx 1.5\ \mu\text{m}$ from finite micro-probe radius.
* Mechanical Stage Backlash: $\sigma_{\text{mech}} \approx 1.2\ \mu\text{m}$ in the micromanipulator lead screws.
* Operator Alignment Parallax: $\sigma_{\text{opt}} \approx 1.5\ \mu\text{m}$ under $200\times$ stereo optics.

With an allowable clearance margin of $m = \pm 5.0\ \mu\text{m}$, the placement tolerance spans approximately $\pm 2.1\,\sigma$, yielding a theoretical single-attempt placement yield of $\approx 96\%$.
2. The Overlap Catastrophe (Binary Scrap):
Unlike amplifier gain, which degrades smoothly with dimensional error, wire placement error produces a catastrophic binary step function:
* Collector Short: If the wire lands $\ge 6\ \mu\text{m}$ to the collector side, subsequent pulse bonding alloys gallium into the $n$-type collector, creating a dead low-impedance short across the collector-base junction ($BV_{\text{CBO}} \to 0\ \text{V}$).
* Emitter Short: If the wire lands $\ge 6\ \mu\text{m}$ to the emitter side, the emitter-base diode is permanently shunted, reducing current gain ($\alpha$) to zero.
* In both cases, the entire header and crystal assembly become total scrap; rework is impossible once the wire is alloyed.
3. Calibrated Touchdown Force Control:
Silicon has extreme hardness (Mohs 7) but zero plasticity at room temperature. If downward force exceeds $5\ \text{mN}$, micro-cracks propagate along $\{111\}$ cleavage planes, severing the base. If force is below $0.2\ \text{mN}$, the wire makes poor electrical contact, resulting in explosive vaporizing arcs during the Step 31 pulse discharge. Technicians utilize a gooseneck S-bend wire spring ($k_{\text{arm}} \approx 15\ \text{N/m}$) that flexes $50\ \mu\text{m}$ upon contact, delivering a calibrated $0.75\ \text{mN}$ preload.

## Position Base Wire's Place in the Process Lineage

Positioning the base wire is step thirty of this project's 1954 silicon grown-junction transistor series — following the electrical location of the base stripe, and preceding the pulse-bonding discharge. It converts the coordinates derived in Step 29 into a physical mechanical landing of the gold-gallium lead wire onto the semiconductor surface. Step thirty-one, pulse-bond the base wire, discharges a precision capacitor bank through this positioned wire to form a permanent low-resistance eutectic alloy contact.