soi (silicon-on-insulator)

Silicon-on-insulator (SOI) technology uses a thin silicon device layer on a buried oxide (BOX) insulator, reducing parasitic capacitance and improving transistor performance for specific applications. Structure: thin Si film (5-100nm) on SiO₂ BOX layer (10-200nm) on Si handle wafer. SOI types: (1) Partially depleted SOI (PDSOI)—thicker Si film (>50nm), body partially depleted, floating body effects; (2) Fully depleted SOI (FDSOI)—ultra-thin body (<10nm), fully depleted channel, excellent electrostatic control; (3) Ultra-thin body and BOX (UTBB)—thin body + thin BOX for back-bias control. Wafer fabrication: (1) Smart Cut (Soitec)—H+ implant, bond, split, polish—dominant commercial process; (2) SIMOX—oxygen implant forms buried oxide (legacy); (3) Bonded SOI—wafer bonding and etch-back. FDSOI advantages: (1) Reduced junction capacitance—BOX isolates S/D from substrate; (2) No random dopant fluctuation—undoped channel; (3) Back-bias control—tune Vt by applying voltage to substrate through thin BOX; (4) Reduced latch-up—complete oxide isolation; (5) Radiation hardness—less charge collection for space/military. FDSOI nodes: GlobalFoundries/STMicroelectronics 22FDX, Samsung 18FDS—competitive with FinFET at equivalent nodes for specific applications. Trade-offs: SOI wafer cost premium ($500+ vs. $100 for bulk Si), self-heating (BOX acts as thermal insulator), limited foundry availability. Applications: IoT (low power with back-bias), automotive (radiation tolerance), RF (reduced substrate coupling), aerospace. SOI provides an alternative scaling path to FinFET for applications where its unique advantages justify the wafer cost premium.