spacer defined multi-patterning

**Spacer-Defined Multi-Patterning** is **the lithographic pitch-multiplication technique that uses conformally deposited thin-film spacers on sacrificial mandrel structures to define features at half or quarter the lithographic pitch, enabling sub-20 nm line/space patterning using 193 nm immersion or EUV lithography tools operating at their native resolution limits**. **Self-Aligned Double Patterning (SADP):** - **Mandrel Formation**: sacrificial mandrel features (amorphous Si, SiO₂, or photoresist) patterned at 2x the final target pitch using standard lithography—e.g., 64 nm pitch mandrels for 32 nm final pitch - **Spacer Deposition**: conformal low-temperature ALD or PECVD deposition of spacer material (SiO₂, SiN, or TiO₂) with thickness equal to target half-pitch (e.g., 16 nm spacer for 32 nm pitch) - **Spacer Etch**: anisotropic RIE removes spacer from horizontal surfaces, leaving vertical spacers on mandrel sidewalls—spacer thickness uniformity of ±0.5 nm (3σ) required for <1 nm CD variation - **Mandrel Pull**: selective wet or dry etch removes mandrel material with >50:1 selectivity to spacer—leaves freestanding spacer lines at 2x density - **Pattern Transfer**: spacer pattern transferred to underlying hardmask by directional etch—final pitch = original spacer thickness × 2 **Self-Aligned Quadruple Patterning (SAQP):** - **Double SADP**: SAQP applies two sequential SADP operations to achieve 4x pitch multiplication—128 nm lithographic pitch yields 32 nm final pitch - **First SADP**: creates spacer pattern at 2x density on first mandrel layer - **Second SADP**: first spacer pattern becomes mandrel for second spacer deposition—second spacer pitch = 1/4 original lithographic pitch - **Total Process Steps**: SAQP requires 3-4x more deposition and etch steps than single exposure—typically 30-50 additional process steps vs EUV single exposure - **Pitch Walk**: systematic CD variation between lines originating from different mandrel edges—even/odd line CD difference must be <0.5 nm for electrical uniformity **Critical Process Parameters:** - **Spacer Thickness Control**: ±0.3 nm (3σ) within-wafer uniformity required—ALD provides superior conformality (<1% loading effect) compared to PECVD - **Spacer Film Stress**: residual stress in spacer film (compressive or tensile) causes line wiggling—stress must be <100 MPa for straight features below 20 nm half-pitch - **Mandrel Profile**: mandrel sidewall angle of 88-90° with rounded tops and flat bottoms ensures symmetric spacer profiles on both sides - **LER Transfer**: mandrel line edge roughness transfers to spacer inner edge—mandrel LER must be <1.5 nm (3σ) to achieve final spacer LER <2 nm - **Etch Selectivity Chain**: each pattern transfer etch requires >20:1 selectivity to underlying layer—SADP needs 3 selective etch steps, SAQP needs 6+ **Design and Layout Implications:** - **Cut Mask Complexity**: spacer-defined patterns produce continuous loops at mandrel ends—separate cut masks using EUV lithography sever unwanted connections - **Tip-to-Tip**: minimum tip-to-tip spacing between cut features of 25-35 nm depends on cut mask overlay accuracy (±1.5 nm) - **Line-End Extensions**: spacer loops require 10-20 nm line-end extensions beyond active device area, consuming layout density - **Unidirectional Routing**: spacer patterning produces only parallel lines in one direction—perpendicular connections require separate block/cut lithography **Cost and Throughput Comparison:** - **SAQP vs EUV**: SAQP uses 3-4 masks plus cuts at 193i cost (~$20M/mask set) vs 1-2 EUV masks at higher per-layer cost—breakeven depends on EUV throughput and availability - **Cycle Time**: SAQP adds 5-8 days to wafer cycle time compared to single EUV exposure—impacts time-to-market and WIP inventory **Spacer-defined multi-patterning remains a critical patterning technique that complements EUV lithography, serving as the primary pitch-multiplication method for tight-pitch metal and via layers where even EUV single exposure cannot achieve the required feature density at the 3 nm node and below.**