Establish the Cache Memory Hierarchy Concept SRAM Enabled

# Establish the Cache-Memory Hierarchy Concept SRAM Enabled

## 10. Establish the Cache-Memory Hierarchy Concept SRAM Enabled

Once dedicated SRAM products existed, system designers could formalize an idea that SRAM's architecture had made practical rather than merely theoretical: organizing memory as a hierarchy of several layers, each faster and smaller than the one below it, with the fastest layer built from SRAM sitting as close to the processor as the physical design allows. The underlying principle is that most programs' real memory accesses cluster heavily around a small, slowly-changing working set at any given moment — a property generally called locality of reference — so a small, fast cache can intercept most accesses before they ever need to reach slower main memory, even though the cache itself holds only a small fraction of the total data a program might touch over its full run. SRAM's combination of low access latency and simple, non-destructive reads is what makes that interception effective in practice: a cache built from a slower or more latency-variable technology would simply reintroduce the delay it was meant to hide. The cache-memory hierarchy as a system-architecture concept and the 6T SRAM cell as a circuit-architecture answer are tightly coupled historically — one made the other worth building at scale.

Locality of Reference Makes a Small Fast Layer Pay Off 10. The Cache-Memory Hierarchy Concept LOCALITY OF REFERENCE Most accesses cluster around a small slowly-changing working set A small cache can intercept most of them Even holding only a fraction of total data WHY SRAM SPECIFICALLY ENABLES IT Low, predictable access latency Non-destructive, no restore delay Interception only works if cache is fast A slow cache reintroduces the delay a system-architecture concept paired tightly with a circuit-architecture answer
A Multi-Layer Hierarchy, Fastest Closest to the Core 10. The Cache-Memory Hierarchy Concept LAYERED MEMORY, EACH FASTER AND SMALLER TOWARD THE CORE Processor core Fast small SRAM cache layer(s), closest to the core Larger DRAM main memory, slower, much higher capacity Secondary storage, slower still, highest capacity the hierarchy concept and the 6T cell emerged together, not independently

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