standard cell characterization

**Standard Cell Library Characterization** is the **process of measuring and modeling static/dynamic behavior of logic cells across voltage/temperature/process corners, producing Liberty (.lib) files that enable accurate timing closure and power analysis in SoC design.** **Liberty (.lib) Format and Structure** - **Liberty File Format**: Text-based specification of cell timing/power characteristics. Defines pins, functions, timing arcs, power tables in human-readable/machine-parseable form. - **Cell Definition**: Each cell (NAND2, NOR3, flip-flop) contains pin descriptions (input/output), function (Boolean logic), timing models, power dissipation. - **Pin Declaration**: Input/output pins specified with direction, capacitance, rise/fall slew rate transitions. Internal pins for special functions (clock, reset). - **Timing Arc**: Connection from one pin to another with delay/slew characterization. Example: NAND2 has A→Y, B→Y delay arcs; flip-flop has D→Q, CLK→Q, SET→Q arcs. **NLDM and CCS Timing Models** - **NLDM (Non-Linear Delay Model)**: Delay and transition time tables indexed by input slew rate and output load capacitance. Cubic polynomial interpolation between table values. - **Delay Formula**: Delay = f(input_slew, output_load). NLDM provides 2D lookup tables (slew × load). Typical table: 5×5 or 7×7 (25-49 characterization points per arc). - **CCS (Composite Current Source)**: Current-based timing model. Cell output modeled as time-varying current source. Accuracy > NLDM for complex waveform scenarios (glitch, crosstalk). - **CCS Advantages**: Captures frequency-dependent behavior, crosstalk noise impact, multi-input switching. Enables better STA accuracy but ~5x larger Liberty files vs NLDM. **Cell Delay and Propagation Arcs** - **Propagation Delay (Tpd)**: Time from input transition 50% to output transition 50%. Monotonically increases with load capacitance and input slew rate. - **Slew Propagation**: Output slew (rise time, fall time) characterized similarly. Impacts fanout gate delays (higher slew = longer downstream delays). - **Delay Dependencies**: Temperature effect (negative temperature coefficient: faster at low T), supply voltage (lower voltage → higher delay), process (Vth variation → delay variation). - **Multi-Input Cells**: Complex cells like muxes, adders have multiple delay arcs (each input → each output). NAND8 has 8 delay paths; characterization combinatorial explosion addressed via clustering/approximation. **Setup/Hold and Clock-to-Q Timing Arcs** - **Setup Time**: Minimum time data must be stable before clock transition. Library specifies setup for all data pins (D, preset, clear) vs clock. - **Hold Time**: Minimum time data must remain stable after clock transition. Hold violations more serious than setup (can't pipeline out of hold). - **Recovery/Removal Times**: For asynchronous inputs (reset, preset). Recovery = minimum time reset must release before clock. Removal = hold-like constraint on reset relative to clock. - **Clock-to-Q Delay**: Delay from clock edge to output switching. Highly load-dependent. Critical for timing budgeting in datapaths. **PVT Characterization Corners** - **Process Variation**: Fast (Vth low, gate oxides thin), slow (opposite), typical corners. SPICE simulations at nominal/extreme process parameters. - **Voltage Variation**: Nominal (1.2V), high (1.35V), low (1.05V). Simulations re-run at each supply voltage. Voltage scaling dramatically affects delay. - **Temperature Variation**: Nominal (25°C), high (85°C or 125°C), low (0°C or -40°C). Temperature affects Vth (negative coefficient) and carrier mobility (positive). - **Typical Characterization**: 3×3×3 (process × voltage × temperature) = 27 Liberty files. High-end libraries may include additional intermediate points. **Statistical (SSTA) Liberty Extensions** - **Statistical Variation Modeling**: SSTA acknowledges not all corners equally likely. Process variation follows normal distribution; characterize sigma (σ). - **Sigma Tables**: Liberty extended with statistical parameters. Cell delay μ (mean) and σ (standard deviation) of delay distribution vs PVT corners. - **Parametric Variation**: Cell delay model includes random variables (Vth mismatch, length variation) beyond fixed corners. Enables better yield prediction. - **Correlation**: Delay variations across multiple cells correlated (spatially correlated process effects). Statistical models capture correlation reducing pessimism in STA. **Characterization Methodology** - **Spice Simulation Setup**: SPICE netlist of cell with transistor-level models (BSIM4, BSIM6). Stimulus: input ramp (multiple slew rates), load capacitor varied (5-500fF typical). - **Measurement Points**: Simulations measure delay, slew, power (switching + leakage) for each (slew, load, corner) combination. - **Table Generation**: Measured data interpolated to regular grid. Polynomial fitting reduces sensitivity to simulation noise. - **Liberty Generation**: Automated tools (Cadence Liberate, Synopsys Characterizer) convert SPICE results to Liberty file with formatting and verification.